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N76E003 datasheet jun 26 , 201 7 page 1 of 267 rev. 1.02 nuvoton 1t 8051 - based microcontroller n76e 003 data s heet
N76E003 datasheet jun 26 , 201 7 page 2 of 267 rev. 1.02 table of c ontents 1. general descripti on ................................ ................................ ................................ ............................... 5 2. features ................................ ................................ ................................ ................................ ....................... 6 3. block diagram ................................ ................................ ................................ ................................ ............ 9 4. pin configuration ................................ ................................ ................................ ................................ ... 10 5. memory organizati on ................................ ................................ ................................ ........................... 14 5.1 program memory ................................ ................................ ................................ ................................ .... 14 5.2 data memory ................................ ................................ ................................ ................................ .......... 16 5.3 on - chip xram ................................ ................................ ................................ ................................ ....... 18 5.4 non - volatile data storage ................................ ................................ ................................ ...................... 18 6. special function register (sfr) ................................ ................................ ................................ ....... 19 6.1 all sfr description ................................ ................................ ................................ ........................ 24 7. i/o port structur e and operation ................................ ................................ ................................ .. 81 7.1 quasi - bidirectional mode ................................ ................................ ................................ ........................ 81 7.2 push - pull mode ................................ ................................ ................................ ................................ ....... 82 7.3 input - only mode ................................ ................................ ................................ ................................ ..... 83 7.4 open - drain mode ................................ ................................ ................................ ................................ ... 83 7.5 read - modify - write instructions ................................ ................................ ................................ .............. 84 7.6 control registers of i/o ports ................................ ................................ ................................ ................. 84 input and output dat a control ................................ ................................ ................................ ..... 85 7.6.1 output mode control ................................ ................................ ................................ .................... 86 7.6.2 input type ................................ ................................ ................................ ................................ .... 88 7.6.3 output slew rate control ................................ ................................ ................................ ............ 90 7.6.4 8. timer/counter 0 a nd 1 ................................ ................................ ................................ ............................ 92 8.1 mode 0 (13 - bit timer) ................................ ................................ ................................ ............................. 95 8.2 mode 1 (16 - bit timer) ................................ ................................ ................................ ............................. 96 8.3 mode 2 (8 - bit auto - reload timer) ................................ ................................ ................................ .......... 96 8.4 mode 3 (two separate 8 - bit timers) ................................ ................................ ................................ ...... 97 9. timer 2 and input capture ................................ ................................ ................................ ................... 99 9.1 auto - reload mode ................................ ................................ ................................ ................................ 103 9.2 co mpare mode ................................ ................................ ................................ ................................ ..... 104 9.3 input capture module ................................ ................................ ................................ ........................... 104 10. timer 3 ................................ ................................ ................................ ................................ ...................... 110 11. wat chdog timer (wdt) ................................ ................................ ................................ ....................... 112 11.1 time - out reset timer ................................ ................................ ................................ ........................ 114 11.2 general purpose timer ................................ ................................ ................................ ...................... 115 12. self wake - up timer (wkt) ................................ ................................ ................................ ................. 117 13. serial port (uar t) ................................ ................................ ................................ ............................... 119 13.1 mode 0 ................................ ................................ ................................ ................................ ................ 124 13.2 mode 1 ................................ ................................ ................................ ................................ ................ 125 13.3 mode 2 ................................ ................................ ................................ ................................ ................ 126 13.4 mode 3 ................................ ................................ ................................ ................................ ................ 127 13.5 baud rate ................................ ................................ ................................ ................................ ........... 127 13.6 framing error detection ................................ ................................ ................................ ..................... 131 13.7 multiprocessor communication ................................ ................................ ................................ .......... 131 13.8 automatic address recognition ................................ ................................ ................................ .......... 132 14. serial periphera l interface (spi) ................................ ................................ ................................ 136 14.1 functional desc ription ................................ ................................ ................................ ........................ 136 14.2 operating modes ................................ ................................ ................................ ................................ 142
N76E003 datasheet jun 26 , 201 7 page 3 of 267 rev. 1.02 master mode ................................ ................................ ................................ ............................ 142 14.2.1 slave mode ................................ ................................ ................................ .............................. 142 14.2.2 14.3 clock formats and data transfer ................................ ................................ ................................ ....... 143 14.4 slave select pin configuration ................................ ................................ ................................ ........... 145 14.5 mode fault detection ................................ ................................ ................................ .......................... 146 14.6 write collision error ................................ ................................ ................................ ............................ 146 14.7 overrun error ................................ ................................ ................................ ................................ ...... 146 14.8 spi interrupt ................................ ................................ ................................ ................................ ........ 147 15. inter - integrated circuit ( i 2 c) ................................ ................................ ................................ ......... 148 15.1 functional descri ption ................................ ................................ ................................ ........................ 148 start and stop condition ................................ ................................ ................................ ... 149 15.1.1 7 - bit address with data format ................................ ................................ ............................... 150 15.1.2 acknowledge ................................ ................................ ................................ ............................ 151 15.1.3 arbitration ................................ ................................ ................................ ................................ . 151 15.1.4 15.2 control registers of i 2 c ................................ ................................ ................................ ...................... 152 15.3 operating modes ................................ ................................ ................................ ................................ 156 master transmitter mode ................................ ................................ ................................ ......... 156 15.3.1 master receiver mode ................................ ................................ ................................ ............. 157 15.3.2 slave receiver mode ................................ ................................ ................................ ............... 158 15.3.3 slave transmitter mode ................................ ................................ ................................ ........... 159 15.3.4 general call ................................ ................................ ................................ ............................. 160 15.3.5 miscellaneous states ................................ ................................ ................................ ............... 161 15.3.6 15.4 typical structure of i 2 c interrupt service routine ................................ ................................ .............. 163 15.5 i 2 c time - out ................................ ................................ ................................ ................................ ....... 167 15.6 i 2 c interrupt ................................ ................................ ................................ ................................ ......... 168 16. pin interrupt ................................ ................................ ................................ ................................ ......... 169 17. pulse width modu lated (pwm) ................................ ................................ ................................ ....... 172 17.1 functional description ................................ ................................ ................................ ........................ 172 pwm generato r ................................ ................................ ................................ ....................... 172 17.1.1 pwm types ................................ ................................ ................................ .............................. 181 17.1.2 operation modes ................................ ................................ ................................ ..................... 183 17.1.3 mask o utput control ................................ ................................ ................................ ................ 186 17.1.4 fault brake ................................ ................................ ................................ ............................... 187 17.1.5 polarity control ................................ ................................ ................................ ........................ 188 17.1.6 17.2 pwm interrupt ................................ ................................ ................................ ................................ ..... 189 18. 12 - bit analog - to - digital converter (a dc) ................................ ................................ ................ 191 18.1 functional description ................................ ................................ ................................ ........................ 191 adc operation ................................ ................................ ................................ ......................... 191 18.1.1 adc conversion triggered by external source ................................ ................................ ...... 192 18.1.2 adc conversion result comparator ................................ ................................ ....................... 193 18.1.3 internal band - gap ................................ ................................ ................................ .................... 194 18.1.4 18.2 control registers of adc ................................ ................................ ................................ ................... 197 19. timed access pro tection (ta) ................................ ................................ ................................ ........ 201 20. interrupt system ................................ ................................ ................................ ................................ 203 20.1 interrupt overview ................................ ................................ ................................ ............................... 203 20.2 enabling interrupts ................................ ................................ ................................ .............................. 204 20.3 interrupt priorities ................................ ................................ ................................ ................................ 207 20.4 interrupt serv ice ................................ ................................ ................................ ................................ .. 211 20.5 interrupt latency ................................ ................................ ................................ ................................ . 212 20.6 external interrupt pins ................................ ................................ ................................ ........................ 212
N76E003 datasheet jun 26 , 201 7 page 4 of 267 rev. 1.02 21. in - application - programming (iap) ................................ ................................ ................................ 214 21.1 iap commands ................................ ................................ ................................ ................................ ... 217 21.2 iap user guide ................................ ................................ ................................ ................................ ... 218 21.3 using flash memory as data storage ................................ ................................ ................................ 218 21.4 in - system - programming (isp) ................................ ................................ ................................ ............ 220 22. power management ................................ ................................ ................................ ............................ 225 22.1 power - down mode ................................ ................................ ................................ ............................. 226 23. clock system ................................ ................................ ................................ ................................ ........ 227 23.1 system clock source s ................................ ................................ ................................ ........................ 227 internal oscillators ................................ ................................ ................................ ................... 2 27 23.1.1 23.2 system clock switching ................................ ................................ ................................ ..................... 228 23.3 system clock divider ................................ ................................ ................................ .......................... 230 23.4 system clock output ................................ ................................ ................................ .......................... 230 24. power monitoring ................................ ................................ ................................ .............................. 232 24.1 power - on reset (por) ................................ ................................ ................................ ...................... 232 24.2 brown - out detection (bod) ................................ ................................ ................................ ............... 233 25. reset ................................ ................................ ................................ ................................ ......................... 238 25.1 power - on reset ................................ ................................ ................................ ................................ . 238 25.2 brown - out reset ................................ ................................ ................................ ................................ 238 25.3 external reset and hard fault reset ................................ ................................ ................................ . 239 25.4 hard fault reset ................................ ................................ ................................ ................................ . 240 25.5 watchdog timer reset ................................ ................................ ................................ ....................... 240 25.6 software r eset ................................ ................................ ................................ ................................ ... 240 25.7 boot select ................................ ................................ ................................ ................................ .......... 242 25.8 reset state ................................ ................................ ................................ ................................ ......... 243 26. auxiliary fe atures ................................ ................................ ................................ ............................. 244 26.1 dual dptrs ................................ ................................ ................................ ................................ ........ 244 26.2 96 - b it uid ................................ ................................ ................................ ................................ ............ 245 27. on - chip - debu gger (ocd) ................................ ................................ ................................ .................... 246 27.1 functional description ................................ ................................ ................................ ........................ 246 27.2 limitation of ocd ................................ ................................ ................................ ................................ 246 28. config bytes ................................ ................................ ................................ ................................ .......... 248 29. in - circuit - programming (icp) ................................ ................................ ................................ .......... 251 30. instruction set ................................ ................................ ................................ ................................ .... 252 31. electrical chara cteristics ................................ ................................ ................................ .......... 256 31.1 absolute maximum ratings ................................ ................................ ................................ ................ 256 31.2 d.c. electrical characteristics ................................ ................................ ................................ ............ 256 31.3 a.c. electrical characteristics ................................ ................................ ................................ ............ 258 31.4 analog electrical characteristics ................................ ................................ ................................ ........ 261 31.5 esd characteristics ................................ ................................ ................................ ............................ 262 31.6 eft characteristics ................................ ................................ ................................ ............................ 262 31.7 flash dc electrical characteristics ................................ ................................ ................................ .... 263 32. package dimensio ns ................................ ................................ ................................ ........................... 264 32.1 20 - pin tssop - 4.4 x 6.5 mm ................................ ................................ ................................ ............ 264 32.2 20 - pin qfn C 3.0 x 3.0 mm ................................ ................................ ................................ ................ 265 33. document revisio n history ................................ ................................ ................................ ............ 266
N76E003 datasheet jun 26 , 201 7 page 5 of 267 rev. 1.02 1. general d escription the N76E003 is a n embedded flash type, 8 - bit high performance 1t 8051 - based microc ontroller. the instruction set is fully compatible with the standard 80c51 and performance enhanced. the N76E003 contains a up to 18k byte s of main flash called aprom , in which the contents of u ser c ode resides. the N76E003 flash supports in - application - pr ogramming (iap) function, which enables on - chip firmware updates. iap al so make s it possible to configure any block of u ser c ode array to be used as non - volatile data storage , which is written by iap and read by iap or movc instruction . there is an additio nal flash called ldrom, in which the boot code normally resides for carrying out in - system - programming ( isp ) . the ldrom size is configurable with a maximum of 4k byte s . to facilitate programming and verification, the flash allows to be programmed and read electronically by parallel writer or in - circuit - programming (icp) . once the code is confirm ed , user can lock the code for security. the N76E003 provides rich peripherals including 256 byte s of sram, 768 byte s of auxiliary ram (xram), up to 18 general purpo se i/o, two 16 - bit timers/counters 0/1 , one 16 - bit timer 2 with three - channel input capture module, one watchdog timer (wdt) , one self wake - u p timer (wkt), one 16 - bit auto - reload timer3 for general purpose or baud rate generator, two uart s with frame error detection and automatic address recognition , one spi, one i 2 c, five enhanced pwm output channels, eight - channel shared pin interrupt for all i/o , and one 12 - bit adc . the peripherals are equipped with 1 8 sources with 4 - level - priority interrupts ca pability. the N76E003 is equipped with three clock sources and supports switching on - the - fly via software. the three clock sources include external clock input, 10 khz internal oscillator, and one 16 mhz internal precise oscillator that is factory trimmed t o 1% at room temperature. the N76E003 provides additional power monitoring detection such as power - on reset and 4 - level brown - out detection , which stabilizes the power - on/off sequence for a high reliability system design. the N76E003 microcontroller operation cons umes a very low power with two economic power modes to reduce power consumption idle and power - down mode, which are software selectable. idle mode turns off the cpu clock but allows continuing peripheral operation. power - down mode stops the whole system clock for minimum power consumption. the system clock of the N76E003 can also be slowed down by software clock divider , which allows for a flexibility between execution performance and power consumption. with high performance cpu core and rich well - designed peripherals, the N76E003 benefits to meet a general purpose, home appliances, or motor control system accomplishment .
N76E003 datasheet jun 26 , 201 7 page 6 of 267 rev. 1.02 2. features ? cpu: C fully static design 8 - bit high performance 1t 80 51 - based cmos microcontroller. C instruction set fully compatible with mcs - 51. C 4 - priority - level interrupts capability. C dual data pointers (dptrs). ? operating : C wide supply voltage from 2.4 v to 5.5v. C wide operating frequency up to 16 mhz . C industrial temperature grade: - 40 to + 10 5 . ? memory: C up to 18k bytes of aprom for user code. C configurable 4k/3k/2k/1k/0 k bytes of ldrom, which provides flexibility to user deve loped boot code . C flash memory accumulated with pages of 128 bytes each. C built - in in - application - programmable ( iap ). C code lock for security. C 256 byte s on - chip ram. C additional 768 byte s on - chip auxiliary ram (xram) accessed by movx instruction. ? clock sources : C 16 mhz high - speed internal oscillator trimmed to 1% when v dd 5.0v, 2% in all conditions. C 10 khz l ow - speed internal oscillator. C external clock input . C on - the - fly clock source switch via software. C programmable system clock divider up to 1/512. ? peripherals : C up to 17 general purpose i/o pins and one input - only pin. all output pins have individual 2 - level slew rate control. C standard interrupt pins ? ? ? ? ? ? ? and ? ? ? ? ? ? ? . C two 16 - bit timers/counters 0 and 1 compatible with standard 805 1 .
N76E003 datasheet jun 26 , 201 7 page 7 of 267 rev. 1.02 C one 16 - bit timer 2 with thre e - channel input capture module a nd 9 input pin can be selected. C one 16 - bit auto - reload timer 3, which can be the baud rate clock source of uarts. C one 16 - bit pwm counter interrupt for timer. C one p rogrammable watchdog timer (wdt) clocked by dedicated 10 khz internal source. C one dedicated self wake - up timer (wkt) for self - timed wake - up for power reduced modes. C two full - duple x uart port s with frame error detection and automatic address recognition . txd and rxd pins of uart0 exchangeable via software. C one spi po rt with master and slave modes , up to 8 mbps when system clock is 16 mhz . C one i 2 c bus with master and slave modes, up to 400 kbps data rate. C three pairs, six channels of pulse width modulator (pwm) output, 10 output pin s can be selected. , up to 16 - bit reso lution, with different modes and fault brake function for motor control. C eight channels of pin interrupt, shared for all i/o ports, with variable configuration of edge/level detection. C one 12 - bit adc , up to 500 k sps converting rate, hardware triggered and conversion result compar e facilitating motor control . ? power management: C two power reduced mode s : i dle and power - down mode . ? power monitor: C brown - out detection (bod) with low power mode available , 4 - level selection , interr upt or reset options. C power - on reset (por) . ? strong esd and eft immunity. ? development tool s : C nuvoton on - chip - debugger (ocd) with keil tm develop ment environment . C nuvoton in - circuit - program m er ( icp ). C nuvoton in - system - programm ing ( i s p ) via uart .
N76E003 datasheet jun 26 , 201 7 page 8 of 267 rev. 1.02 ? part numbers and packages: part number aprom ldro m package N76E003 at20 1 8 k bytes shared with ldrom up to 4 k bytes tssop 20 N76E003aq20 1 8 k bytes shared with ldrom up to 4 k bytes qfn 20
N76E003 datasheet jun 26 , 201 7 page 9 of 267 rev. 1.02 3. block diagram figure 3 - 1 shows the N76E003 functional block diagram and gi ves the outline of the device. user can find all the peripheral functions of the device in the diagram. figure 3 - 1 . function al block diagram 1 t h i g h p e r f o r m a n c e 8 0 5 1 c o r e m a x . 1 8 k b y t e s a p r o m f l a s h 2 5 6 b y t e s i n t e r n a l r a m 7 6 8 b y t e s x r a m ( a u x i l i a r y r a m ) p 0 p 1 p 2 p 3 p w m w a t c h d o g t i m e r c l o c k d i v i d e r s e r i a l p o r t s ( u a r t s ) t i m e r 0 / 1 p o w e r - o n r e s e t a n d b r o w n - o u t d e t e c t i o n i 2 c p 0 [ 7 : 0 ] p 1 [ 7 : 0 ] p 2 0 p 3 0 i n t 1 ( p 1 . 7 ) i n t 0 ( p 3 . 0 ) r x d ( p 0 . 7 o r p 0 . 6 ) t x d ( p 0 . 6 o r p 0 . 7 ) s d a ( p 1 . 4 o r p 1 . 6 ) s c l ( p 1 . 3 o r p 0 . 2 ) p w m 0 ~ p w m 5 ( p 1 . 5 , p 1 . 4 , p 1 . 2 , p 1 . 1 , p 1 . 0 , p 0 . 0 , p 0 . 1 , p 0 [ 3 : 5 ] ) 8 - b i t i n t e r n a l b u s e x t e r n a l i n t e r r u p t t 1 ( p 0 . 0 ) t 0 ( p 0 . 5 ) v d d g n d 1 6 m h z / 1 0 k h z i n t e r n a l r c o s c i l l a t o r r s t 8 8 1 s y s t e m c l o c k p o w e r m a n a g m e n t 1 0 p i n i n t e r r u p t a n y p o r t 8 t i m e r 2 w i t h i n p u t c a p t u r e i c 0 ~ i c 7 ( p 1 . 5 , p 1 [ 2 : 0 ] , p 0 . 0 , p 0 . 1 , p 0 [ 5 : 3 ] ) [ 1 ] p 2 . 0 i s s h a r e d w i t h r s t . [ 2 ] p 3 . 0 i s s h a r e d w i t h x i n . r x d _ 1 ( p 0 . 2 ) t x d _ 1 ( p 1 . 6 ) f b ( p 1 . 4 ) s p i m i s o ( p 0 . 1 ) m o s i ( p 0 . 0 ) s p c l k ( p 1 . 0 ) s s ( p 1 . 5 ) 1 2 - b i t a d c a i n 0 ~ 7 ( p 1 . 7 , p 3 . 0 , p 0 [ 7 : 3 ] , p 0 . 1 ) 8 s t a d c ( p 1 . 3 o r p 0 . 4 ) s e l f w a k e - u p t i m e r m a x . 4 k b y t e s l d r o m f l a s h t i m e r 3 [ 1 ] [ 1 ] x i n [ 2 ] [ 2 ] 9 1
N76E003 datasheet jun 26 , 201 7 page 10 of 267 rev. 1.02 4. pin configuration figure 4 - 1 . pin assignment of tssop - 20 package 1 0 9 2 1 4 3 6 5 8 7 r s t / p 2 . 0 g n d 1 8 1 9 1 6 1 7 1 4 1 5 1 2 1 3 1 1 2 0 v d d n 7 6 e 0 0 3 a t 2 0 [ s d a ] / t x d _ 1 / i c p d a / o c d d a / p 1 . 6 p 1 . 3 / s c l / [ s t a d c ] p 1 . 4 / s d a / f b / p w m 1 p 1 . 1 / p w m 1 / i c 1 / a i n 7 / c l o p 1 . 0 / p w m 2 / i c 2 / s p c l k p 0 . 0 / p w m 3 / i c 3 / m o s i / t 1 p 0 . 1 / p w m 4 / i c 4 / m i s o p 0 . 3 / p w m 5 / i c 5 / a i n 6 p 0 . 4 / a i n 5 / s t a d c / p w m 3 / i c 3 t x d / a i n 3 / p 0 . 6 r x d / a i n 2 / p 0 . 7 i n t 0 / o s c i n / a i n 1 / p 3 . 0 p w m 5 / i c 7 / s s / p 1 . 5 p 0 . 2 / i c p c k / o c d c k / r x d _ 1 / [ s c l ] i n t 1 / a i n 0 / p 1 . 7 p w m 2 / i c 6 / t 0 / a i n 4 / p 0 . 5 p 1 . 2 / p w m 0 / i c 0 1 . [ ] a l t e r n a t e f u n c t i o n r e m a p p i n g o p t i o n ( i f t h e s a m e a l t e r n a t e f u n c t i o n i s s h o w n t w i c e , i t i n d i c a t e s a n e x c l u s i v e c h o i c e n o t a d u p l i c a t i o n o f t h e f u n c t i o n ) .
N76E003 datasheet jun 26 , 201 7 page 11 of 267 rev. 1.02 figure 4 - 2 . pin assignment of qfn - 20 package 2 1 g n d n 7 6 e 0 0 3 a q 2 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 2 1 3 4 5 1 6 1 7 1 8 1 9 2 0 a i n 5 / s t a d c / p w m 3 / i c 3 / p 0 . 4 i n t 0 / o s c i n / a i n 1 / p 3 . 0 r s t / p 2 . 0 t x d / a i n 3 / p 0 . 6 p w m 2 / i c 6 / t 0 / a i n 4 / p 0 . 5 p 1 . 4 / s d a / f b / p w m 1 p 1 . 2 / p w m 0 / i c 0 p 1 . 1 / p w m 1 / i c 1 / a i n 7 / c l o p 1 . 0 / p w m 2 / i c 2 / s p c l k p 1 . 5 / p w m 5 / i c 7 / s s p 0 . 3 / p w m 5 / i c 5 / a i n 6 p 0 . 2 / i c p c k / o c d c k / r x d _ 1 / [ s c l ] p 0 . 1 / p w m 4 / i c 4 / m i s o p 0 . 0 / p w m 3 / i c 3 / m o s i / t 1 p 1 . 3 / s c l / [ s t a d c ] r x d / a i n 2 / p 0 . 7 i n t 1 / a i n 0 / p 1 . 7 g n d [ s d a ] / t x d _ 1 / i c p d a / o c d d a / p 1 . 6 v d d 1 . [ ] a l t e r n a t e f u n c t i o n r e m a p p i n g o p t i o n ( i f t h e s a m e a l t e r n a t e f u n c t i o n i s s h o w n t w i c e , i t i n d i c a t e s a n e x c l u s i v e c h o i c e n o t a d u p l i c a t i o n o f t h e f u n c t i o n ) .
N76E003 datasheet jun 26 , 201 7 page 12 of 267 rev. 1.02 pin n umber symbol multi - function description [ 1 ] tssop20 qfn20 9 5 vdd power supply: supply voltage v dd for operation. 7 3 gnd ground: ground potential. 16 12 p0.0/pwm3/ic3/mosi/t1 p0.0: port 0 bit 0. pwm3: pwm output channel 3. mosi: spi master output/slave in put. ic3 : input capture channel 3 . t 1 : external count input to timer/counter 1 or its toggle output. 17 13 p0.1/pwm4/ic4/miso p0.1: port 0 bit 1. pwm 4 : pwm output channel 4 . ic4 : input capture channel 4 . miso: spi m aster input/slave ou tput. 18 14 p0.2 /icpck/ocdck / rxd _1 /[ scl ] p0.2: port 0 bit 2. icpck: icp clock input. ocdck: ocd clock input. rxd_1: serial port 1 receive input. [ scl ] [ 3 ] : i 2 c clock. 19 15 p0.3 /pwm5/ic5/ain6 p0. 3 : port 0 bit 3 . pwm5: pwm output chan nel ic5: input capture channel 5. ain6: adc input channel 6. 20 16 p0.4/ain5/stadc/pwm3/ ic3 p0.4: port 0 bit 4. a in5 : adc input channel 5. stadc: external start adc trigger pwm3: pwm output channel 3. ic3 : input capture channel 3 . 1 20 p0.5/ pwm2/ic6/t0/ain4 p0.5: port 0 bit 5 . pwm2: pwm output channel 2. ic6: input capture channel 6. t0: external count input to timer/counter 0 or its toggle output. 2 19 p0.6/ txd /ain3 p0.6: port 0 bit 6 . txd [ 2 ] : serial port 0 transm it data output. ain3: adc input channel 3. 3 1 p0.7/rxd/ain2 p0.7: port 0 bit 7 . rxd: serial port 0 receive input. ain2: adc input channel 2. 15 7 p1.0/pwm2 /ic2/spclk p1.0: port 1 bit 0 . pwm2: pwm output channel 2. ic2: i nput capture channel 2. spclk: spi clock. 14 8 p1.1 /pwm1/ic1/ain7/cl o p1.1: port 1 bit 1 pwm1: pwm output channel 1. ic1: input capture channel 1. ain7: adc input channel 7 . clo: system clock output. 13 9 p1.2/ pwm0/ic0 p1.2: p ort 1 bit 2 . pwm0 : pwm output channel 0 . ic0: input capture channel 0 . 12 11 p1.3 /scl/ [ stadc ] p1.3: p ort 1 bit 3 . scl: i 2 c clock.
N76E003 datasheet jun 26 , 201 7 page 13 of 267 rev. 1.02 pin n umber symbol multi - function description [ 1 ] tssop20 qfn20 [ stadc ] [ 4 ] : external start adc trigger 11 10 p1.4 /sda/fb /pwm1 p1.4: p ort 1 bit 4 . sda: i 2 c data. fb: fault brake input. pwm1: pwm output channel 1 . 10 6 p1.5 / pwm5/ic7/ ? ? ? ? p1.5: p ort 1 bit 5 . pwm5: pwm output channel 5 . ic7: input capture channel 7 . ? ? ? ? : spi s lave select input. 8 4 p1.6 /icpda/ocdda /txd _1 /[sda] p1.6: p ort 1 bit 6 . icpda: icp data inpu t or output. ocdat: ocd data input or output. txd_1: serial port 1 transmit data output. [sda] [ 3 ] : i 2 c data. 6 2 p1.7 / ? ? ? ? ? ? ? /ain0 p1.7 : p ort 1 bit 7 . ? ? ? ? ? ? ? : external interrupt 1 input. a in 0: adc input channel 0. 4 18 p2.0 / ? ? ? ? ? ? p2. 0 : port 2 bit 0 input pin available when rpd (config0.2) is programmed as 0. ? ? ? ? ? ? : ? ? ? ? ? ? pin is a schmitt trigger input pin for hardware device reset. a low on this pin reset s the device. ? ? ? ? ? ? pin has an internal pull - up resistor allowing power - on re set by simply connecting an external capacitor to gnd . 5 17 p3.0 / ? ? ? ? ? ? ? /oscin/ain1 p1.0: port 3 bit 0 available when the internal oscillator is used as the system clock . ? ? ? ? ? ? ? : external interrupt 0 input. x in : if the eclk mode is enabled , x in is the external clock input pin. a in 1: adc input channel 1. [1] all i/o pins can be configured as a interrupt pin. this feature is not listed in multi - function description. see section 16. pin interrupt . [ 2 ] txd and rxd pins of uart0 are software exchangeable by uart0px (auxr1.2). [ 3 ] [ i2c ] alternate function remapping option . i2c pins is software switched by i2cpx (i2con.0) . [ 4 ] [ stadc ] alternate function remapping option . stadc pin is software switched by stadcpx (a d ccon1.6) . [ 5 ] piox register decides which pins are pwm or gpio .
N76E003 datasheet jun 26 , 201 7 page 14 of 267 rev. 1.02 5. memory organization a standard 80c51 based microcontroller divides the memory into two different sections, program memory and data memory. the program memory is used to store the instruction codes, whereas the data memory is used to store data or variations during the program execution. the data memory occupies a separate address space from program memory. in N76E003 , there are 256 byte s of internal scratch - pad ram. for many applications those need more internal ram, the N76E003 provides another on - chip 768 byte s of ram, which is called xram, accessed by movx instruction. the whole embedded flash , functioning as program memory, is divided int o three block s: application rom ( aprom ) normal ly for user code, loader rom ( ldrom ) normal ly for boot code , and config bytes for hardware initialization. actually, aprom and ldrom function in the same way but have different size. each block is accumulated p age by page and the page size is 128 byte s. the flash control unit supports erase, program, and read modes. the external writer tools though specific i/o pins , in - application - programming (iap ) , or in - system - programming (isp) can both perform these modes. 5.1 p rogram memory the program memory stores the program codes to execute as shown in figure 5 - 1 . a fter any reset, the cpu begins execution from location 0000h . to service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the program memory. each interrupt is assigned with a fixed location in the program memory. the interrupt causes the cpu to jump to that location with where it commences execution of the interrupt service ro utine (isr). external interrupt 0, for example, is assigned to location 0003h. if external interrupt 0 is going to be used, its service routine should begin at location 0003h. if the interrupt is not going to be used, its service location is available as g eneral purpose program memory. the interrupt service locations are spaced at an interval of eight byte s: 0003h for external interrupt 0, 000bh for timer 0, 0013h for external interrupt 1, 001bh for timer 1, etc. if an interrupt service routine is short eno ugh (as is often the case in control applications), it can reside entirely within the 8 - byte interval. however longer service routines should use a jmp instruction to skip over subsequent interrupt locations if other interrupts are in use. the N76E003 prov ides two internal program memory block s aprom and ldrom. although they both behave the same as the standard 8051 program memory, they play different rules according to
N76E003 datasheet jun 26 , 201 7 page 15 of 267 rev. 1.02 their rom size. the aprom on N76E003 can be up to 18k byte s . user code is normally put i nside. cpu fetches instructions here for execution. the movc instruction can also read this region. the other individual program memory block is called ldrom. the normal function of ldrom is to store the boot code for isp. it can update aprom space and con fig bytes. the code in aprom can also re - program ldrom. for isp details and configuration bit setting related with aprom and ldrom, see section 21.4 in - system - programming (isp) on page 220 . note that aprom and ldrom are hardware individual blocks, consequently if cpu re - boots from ldrom, cpu will automatically re - vector program counter 0000h to the ldrom start address. therefore, cpu accoun ts the ldrom as an independent program memory and all interrupt vectors are independent from aprom. config1 7 6 5 4 3 2 1 0 - - - - - ldsize[2:0] - - - - - r/w factory default value: 1111 11 1 1b bit name description 2:0 ldsize[2:0] ldrom size select th is f ield selects the size of ldrom. 111 = no ld rom . aprom is 1 8 k bytes. 110 = ldrom is 1k bytes. aprom is 1 7 k bytes. 101 = ldrom is 2k bytes. aprom is 1 6 k bytes. 100 = ldrom is 3k bytes. aprom is 15 k bytes. 0xx = ldrom is 4k bytes. aprom is 14 k bytes. figure 5 - 1 . N76E003 program memory map l d r o m 0 0 0 0 h 0 0 0 0 h 0 f f f h / 0 b f f h / 0 7 f f h / 0 3 f f h / 0 0 0 0 h [ 1 ] b s = 0 b s = 1 3 7 f f h / 3 b f f h / 3 f f f h / 4 3 f f h / 4 7 f f h [ 1 ] a p r o m [ 1 ] t h e l o g i c b o u n d a r y a d d r e s s e s o f a p r o m a n d l d r o m a r e d e f i n e d b y c o n f i g 1 [ 2 : 0 ] .
N76E003 datasheet jun 26 , 201 7 page 16 of 267 rev. 1.02 5.2 data memory figur e 5 - 2 shows the internal data memory spaces available on N76E003 . internal data mem ory occupies a separate address space from program memory. the internal data memory can be divided into three blocks. they are the lower 128 byte s of ram, the upper 128 byte s of ram, and the 128 byte s of sfr space. internal data memory addresses are always 8 - bit wide, which implies an address space of only 256 byte s. direct addressing higher than 7fh will access the special function registers (sfrs) space and indirect addressing higher than 7fh will access the upper 128 byte s of ram. although the sfr space and the upper 128 byte s of ram share the same logic address, 80h through ffh, actually they are physically separate entities. direct addressing to distinguish with the higher 128 byte s of ram can only access these sfrs. sixteen addresses in sfr space are e ither byte - addressable or bit - addressable. the bit - addressable sfrs are those whose addresses end in 0h or 8h. the lower 128 byte s of internal ram are present in all 80c51 devices. the lowest 32 byte s as general purpose registers are grouped into 4 banks o f 8 registers. program instructions call these registers as r0 to r7. two bits rs0 and rs1 in the program status word (psw[3:4]) select which register bank is used. it benefits more efficiency of code space, since register instructions are shorter than ins tructions that use direct addressing. the next 16 byte s above the general purpose registers (byte - address 20h through 2fh) form a block of bit - addressable memory space (bit - address 00h through 7fh). the 80c51 instruction set includes a wide selection of si ngle - bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h through 7fh. either direct or indirect addressing can access the lower 128 bytes space. but the upper 128 bytes can only be accessed by indirect addressing . another application implemented with the whole block of internal 256 byte s ram is used for the stack. this area is selected by the stack pointer (sp), which stores the address of the top of the stack. whenever a jm p, call or interrupt is invoked, the return address is placed on the stack. there is no restriction as to where the stack can begin in the ram. by default however, the stack pointer contains 07h at reset. user can then change this to any value desired. the sp will point to the last used value. therefore, the sp will be incremented and then address saved onto the stack. conversely, while popping from the stack the contents will be read first, and then the sp is decreased.
N76E003 datasheet jun 26 , 201 7 page 17 of 267 rev. 1.02 figur e 5 - 2 . data memory map figure 5 - 3 . internal 256 bytes ram addressing u p p e r 1 2 8 b y t e s i n t e r n a l r a m ( i n d i r e c t a d d r e s s i n g ) 0 0 h 7 f h 8 0 h f f h l o w e r 1 2 8 b y t e s i n t e r n a l r a m ( d i r e c t o r i n d i r e c t a d d r e s s i n g ) s f r ( d i r e c t a d d r e s s i n g ) 0 0 0 0 h 0 2 f f h 7 6 8 b y t e s x r a m ( m o v x a d d r e s s i n g ) r e g i s t e r b a n k 0 r e g i s t e r b a n k 1 r e g i s t e r b a n k 2 r e g i s t e r b a n k 3 0 3 0 2 0 1 0 0 0 4 0 5 0 6 0 7 0 b 0 a 0 9 0 8 0 c 0 d 0 e 0 f 1 3 1 2 1 1 1 0 1 4 1 5 1 6 1 7 1 b 1 a 1 9 1 8 1 c 1 d 1 e 1 f 2 3 2 2 2 1 2 0 2 4 2 5 2 6 2 7 2 b 2 a 2 9 2 8 2 c 2 d 2 e 2 f 3 3 3 2 3 1 3 0 3 4 3 5 3 6 3 7 3 b 3 a 3 9 3 8 3 c 3 d 3 e 3 f 4 3 4 2 4 1 4 0 4 4 4 5 4 6 4 7 4 b 4 a 4 9 4 8 4 c 4 d 4 e 4 f 5 3 5 2 5 1 5 0 5 4 5 5 5 6 5 7 5 b 5 a 5 9 5 8 5 c 5 d 5 e 5 f 6 3 6 2 6 1 6 0 6 4 6 5 6 6 6 7 6 b 6 a 6 9 6 8 6 c 6 d 6 e 6 f 7 3 7 2 7 1 7 0 7 4 7 5 7 6 7 7 7 b 7 a 7 9 7 8 7 c 7 d 7 e 7 f d i r e c t o r i n d i r e c t a c c e s s i n g r a m i n d i r e c t a c c e s s i n g r a m 0 0 h 0 7 h 2 8 h 0 8 h 0 f h 1 0 h 1 7 h 1 8 h 1 f h 2 0 h 2 1 h 2 2 h 2 3 h 2 4 h 2 5 h 2 6 h 2 7 h 2 9 h 2 a h 2 b h 2 c h 2 d h 2 e h 2 f h 3 0 h 7 f h 8 0 h f f h 0 0 h f f h b i t - a d d r e s s a b l e g e n e r a l p u r p o s e r e g i s t e r s g e n e r a l p u r p o s e r e g i s t e r s
N76E003 datasheet jun 26 , 201 7 page 18 of 267 rev. 1.02 5.3 on - c hip xram the N76E003 provides additional on - chip 768 byte s auxiliary ram called xram to enlarge the ram space. it occupies the address space from 00h through ffh. the 768 bytes of xram are indirectly accessed by move external instruction movx @dptr or movx @ri. (see the demo code below.) note that the stack poin ter cannot be locate d in any part of xram. xram demo code: mov r0,#23h ;write #5ah to xram with address @23h mov a,#5ah movx @r0,a mov r1,#23h ;read from xram with address @23h movx a,@r1 mov dptr,#0023h ;write #5bh to xram with address @0023h mo v a,#5bh movx @dptr,a mov dptr,#0023h ;read from xram with address @0023h movx a,@dptr 5.4 non - volatile data storage by applying iap, any page of aprom or ldrom can be used as non - volatile data storage. for iap details, please see section 21. in - application - programming (iap) on page 214 .
N76E003 datasheet jun 26 , 201 7 page 19 of 267 rev. 1.02 6. special function reg ister (sfr ) the N76E003 use s special function registers (sfrs) to control and monit or peripherals and their m odes. the sfrs reside in the register locations 80 to ff h and are accessed by direct addressing only. sfrs those end their addresses as 0h or 8h are bit - addressable . it is very useful in cases where user would like to modify a par ticular bit directly without changing other bits via bit - field instructions . all other sfrs are byte - addressable only. the N76E003 contain s all the sfrs present ing in the standard 8051 . however some additional sfrs are built in . therefore, some of unused b yte s in the original 8051 have been given new functions. the sfrs are listed below . to accommodate more than 128 sfrs in the 0x80 to 0xff address space, sfr paging has been implemented. by defaul t, all sfr accesses target sfr p age 0. during device initiali za tion, some sfrs located on sfr p age 1 may need to be accessed. the register sfrs is used to switch sfr addressing page. note that this register has ta write protection. most of sfrs are available on both sfr p age 0 and 1. sfrs C sfr page selection ( ta pr otected ) 7 6 5 4 3 2 1 0 - - - - - - - sfrpage - - - - - - - r/w address: 91h reset value: 0000 0000b bit name description 0 sfrpage sfr page select 0 = instructions access sfr p age 0. 1 = instructions access sfr p age 1. switch sfr page demo code: mov ta ,# 0aa h ; switch to sfr page 1 mov t a,#5 5 h orl sfrs,#01h mov ta ,# 0aa h ; switch to sfr page 0 mov t a,#5 5 h anl sfrs,#0feh
N76E003 datasheet jun 26 , 201 7 page 2 0 of 267 rev. 1.02 table 6 - 1 . sfr memory map sfr p age addr 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f 0 1 f8 scon_1 pdten pdtcnt pmen pmd pordis - eip1 - eiph1 - 0 1 f0 b capcon3 capcon4 spcr sp cr2 spsr spdr - aindids - eiph - 0 1 e8 adccon0 picon pinen pipen pif c2l c2h eip - 0 1 e0 acc adccon1 adccon2 adcdly c0l c0h c1l c1h 0 1 d8 pwmcon0 pwmpl pwm0 l pwm 1 l pwm2l pwm3l piocon0 pwmcon1 0 1 d0 psw pwmph pwm0h pwm1h pwm2h pwm3h pnp fbd 0 1 c8 t2con t2mod rc m p2l rc m p2h tl2 pwm 4 l th2 pwm 5 l adcmpl adcmph 0 1 c0 i2con i2addr adcrl adcrh t3con pwm4h rl3 pwm5h rh3 piocon1 ta 0 1 b8 ip saden saden_1 saddr_1 i2da t i2stat i2clk i2toc 0 1 b0 p3 p0m1 p0s p0m2 p0sr p1m1 p1s p1m2 p1sr p2s - iph pwmintc 0 1 a8 ie saddr wdcon bodcon1 p3m1 p3s p3m2 p3sr iapfd iapcn 0 1 a0 p2 - auxr1 bodcon0 iaptrg iapuen iapal iapah 0 1 98 scon sbuf sbuf_1 eie eie1 - - chpcon 0 1 90 p1 sfrs capcon0 capcon1 capcon2 ckdiv ckswt cken 0 1 88 tcon tmod tl0 tl1 th0 th1 ckcon wkcon 0 1 80 p0 sp dpl dph rctrim0 rctrim 1 rwk pcon unoccupied addresses in the sfr space marked in - are reserved for future use. accessing these areas will ha ve an indeterminate effect and should be avoided.
N76E003 datasheet jun 26 , 201 7 page 21 of 267 rev. 1.02 table 6 - 2 . sfr definitions and reset values symbol definition address /(p age) msb lsb [1] reset value [2] eiph1 extensive interrupt priority high 1 ff h /(0) - - - - - pwkth pt3h psh _ 1 0 0 0 0 0 0 0 0 b eip1 extensive interrupt priority 1 feh /(0) - - - - - pwkt pt3 ps _ 1 0 0 0 0 0 0 0 0 b pmd pwm mask data fch - - pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 0 0 0 0 0 0 0 0 b pmen pwm mask enable fbh - - pmen5 pmen4 pmen3 pmen2 pmen1 pmen 0 0 0 0 0 0 0 0 0 b pdtcnt [4] pwm dead - time counter fah pdtcnt[7:0] 0 0 0 0 0 0 0 0 b pdten [4] pwm dead - time enable f9h - - - pdtcnt.8 - pdt45en pdt23en pdt01en 0 0 0 0 0 0 0 0 b scon _ 1 serial port 1 control f8h (ff) sm0 _ 1/ fe _ 1 (fe) sm1 _ 1 (fd) sm2 _ 1 (fc) ren _ 1 (fb) tb8 _ 1 ( fa) rb8 _ 1 (f9) ti _ 1 (f8) ri _ 1 0 0 0 0 0 0 0 0 b eiph extensive interrupt priority high f7h pt2h pspih p fb h pwdth ppwmh pcaph ppih pi2ch 0 0 0 0 0 0 0 0 b aindids adc channel digital input disable f6h p11dids p03dids p04dids p05dids p06dids p07dids p30dids p17dids 0000 0 0 0 0 b spdr spi data f5h (0) spdr[7:0] 0 0 0 0 0 0 0 0 b spsr spi status f4h spif wcol spiovf modf dismodf - - - 0 0 0 0 0 0 0 0 b spcr spi control f3h (0) ssoe spien lsbfe mstr cpol cpha spr[1:0] 0 0 0 0 0 0 0 0 b sp cr2 spi control 2 f3h(1) - - - - - - spis[1:0] 0 0 0 0 0 0 0 0 b capcon4 input capture control 4 f2h - - - - cap23 cap22 cap21 cap20 0 0 0 0 0 0 0 0 b capcon3 input capture control 3 f1h cap13 cap12 cap11 cap10 cap03 cap02 cap01 cap00 0 0 0 0 0 0 0 0 b b b register f0h (f7) b.7 (f6) b.6 (f5) b.5 (f4) b.4 (f3) b.3 (f2) b.2 (f1) b.1 (f0) b.0 0 0 0 0 0 0 0 0 b eip extensive interrupt priority efh pt2 pspi p fb pwdt ppwm pcap ppi pi2c 0 0 0 0 0 0 0 0 b c2h input capture 2 high byte eeh c2h[7:0] 0 0 0 0 0 0 0 0 b c2l input capture 2 low byte edh c2l[7:0] 0 0 0 0 0 0 0 0 b pif pin interrupt flag ech pif7 pif6 pi f5 pif4 pif3 pif2 pif1 pif0 0 0 0 0 0 0 0 0 b pipen pin interrupt high level/rising edge enable ebh pipen7 pipen6 pipen5 pipen4 pipen3 pipen2 pipen1 pipen0 0 0 0 0 0 0 0 0 b pinen pin interrupt low level/falling edge enable eah pinen7 pinen6 pinen5 pinen4 pinen3 pinen 2 pinen1 pinen0 0 0 0 0 0 0 0 0 b picon pin interrupt control e9h pit67 pit45 pit3 pit2 pit1 pit0 pips[1:0] 0 0 0 0 0 0 0 0 b adccon0 adc control 0 e8h (ef) adcf (ee) adcs (ed) etgsel1 (ec) etgsel0 (eb) adchs3 (ea) adchs2 (e9) adchs1 (e8) adchs0 0 0 0 0 0 0 0 0 b c1h input capture 1 high byte e7h c1h[7:0] 0 0 0 0 0 0 0 0 b c1l input capture 1 low byte e6h c1l[7:0] 0 0 0 0 0 0 0 0 b c0h input capture 0 high byte e5h c0h[7:0] 0 0 0 0 0 0 0 0 b c0l input capture 0 low byte e4h c0l[7:0] 0 0 0 0 0 0 0 0 b adcdly adc trigger delay e3h adcdly[7:0] 0 0 0 0 0 0 00b adccon2 adc control 2 e2h ad fb en adcmpop adcmpen adcmpo - - - adcdly.8 0 0 0 0 0 0 0 0 b adccon1 adc control 1 e1h - stadcpx - - etgtyp[1:0] adcex adcen 0 0 0 0 0 0 0 0 b acc accumulator e0h (e7) acc.7 (e6) acc.6 (e5) acc.5 (e4) acc.4 (e3) acc.3 (e2) acc.2 (e1) a cc.1 (e0) acc.0 0 0 0 0 0 0 0 0 b pwmcon1 pwm control 1 dfh pwmmod[1:0] gp pwmtyp fb inen pwmdiv[2:0] 0 0 0 0 0 0 0 0 b piocon0 pwm i/o switch 0 deh - - pio05 pio04 pio03 pio02 pio01 pio00 0 0 0 0 0 0 0 0 b pwm 3 l pwm 3 duty low byte ddh pwm 3 [7:0] 0 0 0 0 0 0 0 0 b pwm 2 l pwm 2 duty l ow byte dch pwm 2 [7:0] 0 0 0 0 0 0 0 0 b pwm 1 l pwm 1 duty low byte dbh pwm 1 [7:0] 0 0 0 0 0 0 0 0 b pwm0l pwm0 duty low byte dah pwm0[7:0] 0 0 0 0 0 0 0 0 b pwmpl pwm period low byte d9h pwmp[7:0] 0 0 0 0 0 0 0 0 b pwmcon0 pwm control 0 d8h (df) pwmrun (de) load (dd) pwmf (dc) clrpw m (db) - (da) - (d9) - (d8) - 0 0 0 0 0 0 0 0 b fb d brake data d7h fb f fb inls fb d5 fb d4 fb d3 fb d2 fb d1 fb d0 0 0 0 0 0 0 0 0 b pnp pwm negative polarity d6h - - pnp5 pnp4 pnp3 pnp2 pnp1 pnp0 0 0 0 0 0 0 0 0 b pwm3h pwm3 duty high byte d5h pwm3[15:8] 0 0 0 0 0 0 0 0 b pwm2h pwm2 du ty high byte d4h pwm2[15:8] 0 0 0 0 0 0 0 0 b pwm1h pwm1 duty high byte d3h pwm1[15:8] 0 0 0 0 0 0 0 0 b pwm0h pwm0 duty high byte d2h pwm0[15:8] 0 0 0 0 0 0 0 0 b pwmph pwm period high byte d1h pwmp[1 5 :8] 0 0 0 0 0 0 0 0 b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) - (d0) p 0 0 0 0 0 0 0 0 b adcmph adc compare high byte cfh adcmp[ 11 : 4 ] 0 0 0 0 0 0 0 0 b adcmpl adc compare low byte ceh - - - - adcmp[3:0] 0 0 0 0 0 0 0 0 b pwm5l pwm5 duty low byte cdh(1) pwm5[7:0] 0 0 0 0 0 0 0 0 b th2 timer 2 high byte cdh (0) th2[7 :0] 0 0 0 0 0 0 0 0 b pwm4l pwm4 duty low byte cch(1) pwm4[7:0] 0 0 0 0 0 0 0 0 b
N76E003 datasheet jun 26 , 201 7 page 22 of 267 rev. 1.02 table 6 - 2 . sfr definitions and reset values symbol definition address /(p age) msb lsb [1] reset value [2] tl2 timer 2 low byte cch (0) tl2[7:0] 0 0 0 0 0 0 0 0 b rcmp2h timer 2 compare high byte cbh rcmp2h[7:0] 0 0 0 0 0 0 0 0 b rcmp2l timer 2 compare low byte cah (0) rcmp2l[7:0] 0 0 0 0 0 0 0 0 b t2mod timer 2 mode c9h lden t2div[2:0] capcr cmpcr ldts[1:0] 0 0 0 0 0 0 0 0 b t2con timer 2 control c8h (cf) tf2 (ce) - (cd) - (cc) - (cb) - (ca) tr2 (c9) - (c8) ? ? ? ? ? ? 0 0 0 0 0 0 0 0 b ta timed access protection c7h ta[7:0] 0 0 0 0 0 0 0 0 b piocon1 pwm i/o switch 1 c6h(1) - - pio1 5 - pio13 pio12 pio11 - 0 0 0 0 0 0 0 0 b rh3 timer 3 reload high byte c6h (0) rh3[7:0] 0 0 0 0 0 0 0 0 b pwm5h pwm5 duty high byte c5h(1) pwm5[15:8] 0 0 0 0 0 0 0 0 b rl3 timer 3 reload low byte c5h (0) rl3[7:0] 0 0 0 0 0 0 0 0 b pwm4h pwm4 duty high byte c4h(1) pwm4[15:8] 0 0 0 0 0 0 00b t3con timer 3 control c4h (0) smod _ 1 smod0 _ 1 brck tf3 tr3 t3ps[2:0] 0 0 0 0 0 0 0 0 b adcrh adc result high byte c3h adcr[11:4] 0 0 0 0 0 0 0 0 b adcrl adc result low byte c2h - - - - adcr[3:0] 0 0 0 0 0 0 0 0 b i2addr i 2 c own slave address c1h i2addr[7:1] gc 0 0 0 0 0 0 0 0 b i2con i 2 c control c0h (c7) - (c6) i2cen (c4) sta (c4) sto (c3) si (c2) aa (c1) - (c0) i2cpx 0 0 0 0 0 0 0 0 b i2toc i 2 c time - out counter bfh - - - - - i2tocen div i2tof 0 0 0 0 0 0 0 0 b i2clk i 2 c clock beh i2clk[7:0] 0 0 0 0 1 0 01 b i2stat i 2 c status bdh i2stat[7:3] 0 0 0 1 1 1 1 1 0 0 0 b i2dat i 2 c data bch i2dat[7:0] 0 0 0 0 0 0 0 0 b saddr _ 1 slave 1 address bbh saddr _ 1[7:0] 0 0 0 0 0 0 0 0 b saden _ 1 slave 1 address mask bah saden _ 1[7:0] 0 0 0 0 0 0 0 0 b saden slave 0 address mask b9h saden[7:0] 0 0 0 0 0 0 0 0 b ip interrupt priority b8h (bf) - (be) padc (bd) pbod (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 0 0 0 0 0 0 0 0 b pwmintc pwm interrupt control b 7h(1) - - inttyp1 inttyp0 - intsel2 intsel1 intsel0 0 0 0 0 0 0 0 0 b iph interrupt priority high b7h (0) - padch pbodh psh pt1h px1h pt0h px0h 0 0 0 0 0 0 0 0 b p2s p2 0 s etting and timer0/1 output enable b5h p20up - - - t1oe t0oe - p2s.0 0 0 0 0 0 0 0 0 b p1sr p1 slew rate b4h/(1) p1sr.7 p1sr.6 p1sr.5 p1sr.4 p1sr.3 p1sr.2 p1sr.1 p1sr.0 0 0 0 0 0 0 0 0 b p1m2 p1 mode select 2 b4h/(0) p1m2.7 p1m2.6 p1m2.5 p1m2.4 p1m2.3 p1m2.2 p 1m2.1 p1m2.0 0 0 0 0 0 0 0 0 b p1s p1 schmitt trigger input b3h/(1) p1s.7 p1s.6 p1s.5 p1s.4 p1s.3 p1s.2 p1s.1 p1s.0 0 0 0 0 0 0 0 0 b p1m1 p1 mode select 1 b3h/(0) p1m1.7 p1m1.6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 1 1 1 1 1 1 1 1 b p0sr p0 slew rate b2h/(1) p0sr.7 p0s r.6 p0sr.5 p0sr.4 p0sr.3 p0sr.2 p0sr.1 p0sr.0 0 0 0 0 0 0 0 0 b p0m2 p0 mode select 2 b2h/(0) p0m2.7 p0m2.6 p0m2.5 p0m2.4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 0 0 0 0 0 0 0 0 b p0s p0 schmitt trigger input b1h/(1) p0s.7 p0s.6 p0s.5 p0s.4 p0s.3 p0s.2 p0s.1 p0s.0 0 0 0 0 0 0 0 0 b p0m 1 p0 mode select 1 b1h/(0) p0m1.7 p0m1.6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 1 1 1 1 1 1 1 1 b p3 port 3 b0h (b7) 0 (b6) 0 (b5) 0 (b4) 0 (b3) 0 (b2) 0 (b1) 0 (b0) p3.0 output latch, 0 0 0 0 0 0 0 1 b input, 0000 000xb [3] iapcn iap control afh iapa[17:16] foen fc en fctrl[3:0] 0 0 1 1 0 0 0 0 b iapfd iap flash data aeh iapfd[7:0] 0 0 0 0 0 0 0 0 b p3sr p3 slew rate adh/(1) - - - - - - - p3sr.0 0 0 0 0 0 0 0 0 b p3m2 p3 mode select 2 adh/(0) - - - - - - - p3m2.0 0 0 0 0 0 0 0 0 b p3s p3 schmitt trigger input ach/(1) - - - - - - - p3s.0 000 0 0 0 0 0 b p3m1 p3 mode select 1 ach/(0) - - - - - - - p3m1.0 0 0 0 0 0 0 0 1 b bodcon1 [4] brown - out detection control 1 abh - - - - - lpbod[1:0] bodflt por, 0 0 0 0 0 0 0 1 b others, 0 0 0 0 0 u u u b wdcon [4] watchdog timer control aah wdt r wdclr wdtf widpd wdtrf wdps[2:0] p or, 0 0 0 0 0 1 1 1 b wdt, 0 0 0 0 1 u u u b others, 0 0 00 u u u u b
N76E003 datasheet jun 26 , 201 7 page 23 of 267 rev. 1.02 table 6 - 2 . sfr definitions and reset values symbol definition address /(p age) msb lsb [1] reset value [2] saddr slave 0 address a9h saddr[7:0] 0 0 0 0 0 0 0 0 b ie interrupt enable a8h (af) ea (ae) eadc (ad) ebod (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0 0 0 0 0 0 0 0 b iapah iap address high byte a7h iapa[15:8] 0000 0 0 0 0 b iapal iap address low byte a6h iapa[7:0] 0 0 0 0 0 0 0 0 b iapuen [4] iap update enable a5h - - - - - cfuen lduen apuen 0000 0000b iaptrg [4] iap trigger a4h - - - - - - - iapgo 0000 0000b bodcon0 [4] brown - out detection control 0 a3h boden [5] - bov[1:0] [5 ] bof [6] borst [5] borf bos [ 7 ] por, cccc xc0xb bod, uuuu xu1xb others, uuuu xuuxb auxr1 auxiliary register 1 a2h swrf rstpinf hardf - gf2 uart0px 0 dps por, 0 0 0 0 0 0 0 0 b software, 1 u 0 0 0 0 0 0 b ? ? ? ? ? ? pin, u 1 0 0 0 0 0 0 b others, uu u 0 0000b p2 port 2 a0h (a7) 0 (a6) 0 (a5) 0 (a4) 0 (a3) 0 (a2) 0 (a1) 0 (a0) p2.0 output latch, 0 0 0 0 0 0 0 x b input, 0000 000xb [3] chpcon [4] chip control 9fh swrst iapff - - - - bs [ 5 ] iapen software, 0 0 0 0 0 0 u 0 b others, 0 0 0 0 0 0 c 0 b eie1 extensive interrupt enable 1 9ch - - - - - ewkt et3 es _ 1 0 0 0 0 0 0 0 0 b eie extensive interrupt enable 9bh et2 espi efb ewdt epwm ecap epi ei2c 0 0 0 0 0 0 0 0 b sbuf _ 1 serial port 1 data buffer 9ah sbuf _ 1[7:0] 0 0 0 0 0 0 0 0 b sbuf serial port 0 data buffer 99h sbuf[7:0] 0 0 0 0 0 0 0 0 b scon serial port 0 control 98h (9f) sm0/f e (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 0 0 0 0 0 0 0 0 b cken [4] clock enable 97h exten[1:0] hircen - - - - ckswtf 0 0 1 1 0 0 0 0 b ckswt [4] clock switch 96h - - hircst - eclkst osc[1:0] - 0 0 1 1 0 0 0 0 b ckdiv clock divider 95h ckdiv[7:0] 0 0 0 0 0 0 00b capcon2 input capture control 2 94h - enf2 enf1 enf0 - - - - 0 0 0 0 0 0 0 0 b capcon1 input capture control 1 93h - - cap2ls[1:0] cap1ls[1:0] cap0ls[1:0] 0 0 0 0 0 0 0 0 b capcon0 input capture control 0 92h - capen2 capen1 capen0 - capf2 capf1 capf0 0 0 0 0 0 0 0 0 b sfrs [4] sfr page selection 91h - - - - - - - sfrpsel 0 0 0 0 0 0 0 0 b p1 port 1 90h (97) p1.7 (96) p1.6 (95) p1.5 (94) p1.4 (93) p1.3 (92) p1.2 (91) p1.1 (90) p1.0 output latch, 1 1 1 1 1 1 1 1 b input, xxxx xxxxb [3] wkcon self wake - up timer control 8fh - - - wktf w ktr wkps[2:0] 0 0 0 0 0 0 0 0 b ckcon clock control 8eh - pwmcks - t1m t0m - cloen - 0 0 0 0 0 0 0 0 b th1 timer 1 high byte 8dh th1[7:0] 0 0 0 0 0 0 0 0 b th0 timer 0 high byte 8ch th0[7:0] 0 0 0 0 0 0 0 0 b tl1 timer 1 low byte 8bh tl1[7:0] 0 0 0 0 0 0 0 0 b tl0 timer 0 low byte 8ah tl0[7:0] 0 0 0 0 0 0 0 0 b tmod timer 0 and 1 mode 89h gate ? m1 m0 gate ? m1 m0 0 0 0 0 0 0 0 0 b tcon timer 0 and 1control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0 0 0 0 0 0 0 0 b pcon power control 87h smod smod0 - pof gf1 gf0 pd idl por, 0 0 0 1 0 0 0 0 b others, 0 0 0 u 0 0 0 0 b rwk self wake - up timer reload byte 86h rwk[7:0] 0 0 0 0 0 0 0 0 b rctrim1 internal rc trim value low byte 85h - - - - - - - hirctrim [0] 0 0 0 0 0 0 0 0 b rctrim0 internal rc trim value 84 h hirctrim [8:1] 0 0 0 0 0 0 0 0 b
N76E003 datasheet jun 26 , 201 7 page 24 of 267 rev. 1.02 table 6 - 2 . sfr definitions and reset values symbol definition address /(p age) msb lsb [1] reset value [2] high byte dph data pointer high byte 83h dptr[15:8] 0 0 0 0 0 0 0 0 b dpl data pointer low byte 82h dptr[7:0] 0 0 0 0 0 0 0 0 b sp stack pointer 81h sp[7:0] 0 0 0 0 0 1 1 1 b p0 port 0 80h (87) p0.7 (86) p0.6 (85) p0.5 (84) p0.4 (83) p0.3 (82) p0.2 (81) p0.1 (80) p0.0 output latch, 1 1 1 1 1 1 1 1 b input, xxxx xxxxb [3] [1] ( ) item means the bit address in bit - addressable sfrs. [2] reset value symbol description. 0: logic 0 ; 1: logic 1 ; u: unchanged ; c: see [5] ; x: see [3] , [6] , and [ 7 ] . [3] all i/o pins are default input - only mode (floa ting) after reset. reading back p2.0 is always 0 if rpd (config 0.2 ) remains un - programmed 1 . [4] these sfrs have ta protected writing. [5] these sfrs have bits those are initialized according to config values after specified resets . [6] bof reset value de pends on different setting of config2 and v dd voltage level. please check table 24 - 1 . [ 7 ] bos is a read - only flag decided by v dd level while brown - out detection is enabled. b its marked in - are reserved for fut ure use. they must be kept in their own initial states. accessing these bits may cause an unpredictable effect. 6.1 all sfr description following list all sfr description. for each sfr define also list in function ip chapter. p0 C port 0 (bit - addressable) 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 r/w r/w r/w r/w r/w r/w r/w r/w address: 80h reset value: 1111 1111b bit name description 7:0 p0[7:0] port 0 port 0 is an maximum 8 - bit general purpose i/o port. sp C stack pointer 7 6 5 4 3 2 1 0 sp[7:0] r/w address: 81h reset value: 0000 0111b bit name description 7:0 sp[7:0] stack pointer the stack pointer stores the scratch - pad ram address where the stack begins. it is incremented before data is stored du ring push or call instructions. note t hat the default value of sp is 07h. this causes the stack to begin at location 08h.
N76E003 datasheet jun 26 , 201 7 page 25 of 267 rev. 1.02 dpl C data pointer low byte 7 6 5 4 3 2 1 0 dpl[7:0] r/w address: 82h reset value: 0000 0000b bit name description 7:0 dpl[7:0] data pointer low byte this is the low byte of 16 - bit data pointer. dpl combined with dph serve as a 16 - bit data pointer dptr to access indirect addressed ram or program memory. dps (auxr1.0) bit decides which data pointer, dptr or dptr1, is activated. dph C data pointer high byte 7 6 5 4 3 2 1 0 dph[7:0] r/w address: 83h reset value: 0000 0000b bit name description 7:0 dph[7:0] data pointer high byte this is the high byte of 16 - bit data pointer. dph combined with dpl serve as a 16 - bit data pointer dptr to access indirect addressed ram or p rogram memory. dps (auxr1.0) bit decides which data pointer, dptr or dptr1, is activated. rwk C self wake - up timer reload byte 7 6 5 4 3 2 1 0 rwk[7:0] r/w address: 86h reset value: 0000 0000b bit name description 7:0 rwk[7:0] wkt reload byte i t holds the 8 - bit reload value of wkt . note that rwk should not be ffh if the pre - scale is 1/1 for implement limitation. pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7 smod serial port 0 double baud rate enable setting this bit doubles the serial port baud rate when uart0 is in mode 2 or when timer 1 overflow is used as t he baud rate source of uart0 mode 1 or 3. see table 13 - 1 . serial port 0 mode description for details. 6 smod0 serial port 0 framing error flag access enable 0 = scon.7 accesses to sm0 bit. 1 = scon.7 accesses to f e bit.
N76E003 datasheet jun 26 , 201 7 page 26 of 267 rev. 1.02 bit name description 4 pof power - on reset flag this bit will be set as 1 after a power - on reset. it indicates a cold reset, a power - on reset complete. this bit remains its value after any other resets. this flag is recommended to be cleared via software. 3 gf1 general purpose flag 1 the g eneral purpose flag that can be set or cleared by user via software. 2 gf0 general purpose flag 0 the g eneral purpose flag that can be set or cleared by user via software. 1 pd power - down mode setting this bit puts cpu into power - dow n mode. under this mode, both cpu and peripheral clocks stop and program counter (pc) suspends. it provides the lowest power consumption. after cpu is woken up from power - down, this bit will be automatically cleared via hardware and the program continue ex ecuting the interrupt service routine (isr) of the very interrupt source that woke the system up before. after return from the isr, the device continues execution at the instruction, which follows the instruction that put the system into power - down mode. n ote that if idl bit and pd bit are set simultaneously, cpu will enter power - down mode. then it does not go to idle mode after exiting power - down. 0 idl idle mode setting this bit puts cpu into idle mode. under this mode, the cpu clock stops and program co unter (pc) suspends but all peripherals keep activated . after cpu is woken up from idle, this bit will be automatically cleared via hardware and the program continue executing the isr of the very interrupt source that woke the system up before. after retur n from the isr, the device continues execution at the instruction which follows the instruction that put the system into idle mode. tcon C timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r (level) r/w (edge) r/w r (level) r/w (edge) r/w address: 88h reset value: 0000 0000b bit name description 7 tf1 timer 1 overflow flag this bit is set when timer 1 overflows. it is automatically cleared by hardware when the program executes the timer 1 interrupt service routine. this bit can be set or cleared by software. 6 tr1 timer 1 run control 0 = timer 1 disabled . clearing this bit will halt timer 1 and the current count will be preserved in th1 and tl1. 1 = timer 1 e nabled. 5 tf0 timer 0 overflow flag this bit is set when timer 0 overflows. it is automatically cleared via hardware when the program executes the timer 0 interrupt service routine. this bit can be set or cleared by software. 4 tr0 timer 0 run control 0 = timer 0 disabled . clearing this bit wil l halt timer 0 and the current count will be preserved in th0 and tl0. 1 = timer 0 e nabled.
N76E003 datasheet jun 26 , 201 7 page 27 of 267 rev. 1.02 bit name description 3 ie1 external interrupt 1 edge flag if it1 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. it remain set until clea red via software or cleared by hardware in the beginning of its interrupt service routine. if it1 = 0 (low level trigger), this flag follows the inverse of the ? ? ? ? ? ? ? input sig n als logic level. software cannot control it. 2 it1 external interrupt 1 type select this bit selects by which type that ? ? ? ? ? ? ? is triggered. 0 = ? ? ? ? ? ? ? is low level triggered. 1 = ? ? ? ? ? ? ? is falling edge triggered. 1 ie0 external interrupt 0 edge flag if it0 = 1 (falling edge trigger), this flag will be set by hardware when a falli ng edge is detected. it remain set until cleared via software or cleared by hardware in the beginning of its interrupt service routine. if it0 = 0 (low level trigger), this flag follows the inverse of the ? ? ? ? ? ? ? input sig n als logic level. software cannot control it. 0 it0 external interrupt 0 type select this bit selects by which type that ? ? ? ? ? ? ? is triggered. 0 = ? ? ? ? ? ? ? is low level triggered. 1 = ? ? ? ? ? ? ? is falling edge triggered. tmod C timer 0 and 1 mode 7 6 5 4 3 2 1 0 gate ? m1 m0 gate ? m1 m0 r/w r/w r/w r/w r/w r/w r/w r/w address: 89h reset value: 0000 0000b bit name description 7 gate timer 1 gate control 0 = timer 1 will clock when tr1 is 1 regardless of ? ? ? ? ? ? ? logic level. 1 = timer 1 will clock only when tr1 is 1 and ? ? ? ? ? ? ? is logi c 1 . 6 ? timer 1 counter/timer select 0 = timer 1 is incremented by internal system clock. 1 = timer 1 is incremented by the falling edge of the external pin t1. 5 m1 timer 1 mode select m 1 m 0 timer 1 mode 0 0 mode 0: 13 - bit timer/counter 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th1 1 1 mode 3 : timer 1 halted 4 m0 3 gate timer 0 gate control 0 = timer 0 will clock when tr 0 is 1 regardless of ? ? ? ? ? ? ? logic level. 1 = timer 0 will clock only when tr 0 is 1 and ? ? ? ? ? ? ? is logic 1 . 2 ? timer 0 counter/timer select 0 = timer 0 is incremented by internal system clock. 1 = timer 0 is incremented by the falling edge of the external pin t0. 1 m1 timer 0 mode select
N76E003 datasheet jun 26 , 201 7 page 28 of 267 rev. 1.02 bit name description 0 m0 m 1 m 0 timer 0 mode 0 0 mode 0: 13 - bit timer/counter 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th0 1 1 mode 3 : tl0 as a 8 - bit timer/counter and th0 as a 8 - bit timer tl0 C timer 0 low byte 7 6 5 4 3 2 1 0 tl0[7:0] r/w address: 8ah rese t value: 0000 0000b bit name description 7:0 tl0[7:0] timer 0 low byte the tl0 register is the low byte of the 16 - bit counting register of timer 0. tl1 C timer 1 low byte 7 6 5 4 3 2 1 0 tl1[7:0] r/w address: 8bh reset value: 0000 0000b bit name descr iption 7:0 tl1[7:0] timer 1 low byte the tl 1 register is the low byte of the 16 - bit counting register of timer 1 . th0 C timer 0 high byte 7 6 5 4 3 2 1 0 th0[7:0] r/w address: 8ch reset value: 0000 0000b bit name description 7:0 th0[7:0] timer 0 high byte the t h 0 register is the high byte of the 16 - bit counting register of timer 0. th1 C timer 1 high byte 7 6 5 4 3 2 1 0 th1[7:0] r/w address: 8dh reset value: 0000 0000b bit name description 7:0 th1[7:0] timer 1 high byte the t h1 register is the h igh byte of the 16 - bit counting register of timer 1 .
N76E003 datasheet jun 26 , 201 7 page 29 of 267 rev. 1.02 ckcon C clock control 7 6 5 4 3 2 1 0 - pwmcks - t1m t0m - cloen - - r/w - r/w r/w - r/w - address: 8eh reset value: 0000 0000b bit name description 6 pwmcks pwm clock source select 0 = the clock so urce of pwm is the system clock f sys . 1 = the clock source of pwm is the overflow of timer 1. 4 t1m timer 1 clock mode select 0 = the clock source of timer 1 is the system clock divided by 12. it maintains standard 8051 compatibility. 1 = the clock source of timer 1 is direct the system clock. 3 t0m timer 0 clock mode select 0 = the clock source of timer 0 is the system clock divided by 12. it maintains standard 8051 compatibility. 1 = the clock source of timer 0 is direct the system clock. 1 cloen syste m clock output enable 0 = system clock output disabled. 1 = system clock output enabled from clo pin (p 1 . 1 ). wkcon C self wake - up timer control 7 6 5 4 3 2 1 0 - - - wktf wktr wkps[2:0] - - - r/w r/w r/w address: 8fh reset value: 0000 0000b bit name de scription 4 wktf wkt overflow flag this bit is set when wkt overflows. if the wkt interrupt and the global interrupt are enabled, setting this bit will make cpu execute wkt interrupt service routine. this bit is not automatically cleared via hardware and should be cleared via software. 3 wktr wkt run control 0 = wkt is halted. 1 = wkt starts running. note that the reload register rwk can only be written when wkt is halted ( wktr bit is 0). if wkt is written while wktr is 1, result is unpredictable. 2:0 wk ps[2:0] wkt pre - scalar these bits determine the pre - scale of wkt clock. 000 = 1/1. 001 = 1/4. 010 = 1/16. 011 = 1/64. 100 = 1/256. 101 = 1/512. 110 = 1/1024. 111 = 1/2048.
N76E003 datasheet jun 26 , 201 7 page 30 of 267 rev. 1.02 p1 C port 1 (bit - addressable) 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p 1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: 90h reset value: 1111 1111b bit name description 7:0 p1 [7:0] port 1 port 1 is an maximum 8 - bit general purpose i/o port. sfrs C sfr page selection ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - sfrpage - - - - - - - r/w address: 91h reset value: 0000 0000b bit name description 0 sfrpage sfr page select 0 = instructions access sfr page 0. 1 = instructions access sfr page 1. capcon0 C input capture control 0 7 6 5 4 3 2 1 0 - capen2 capen1 capen0 - capf2 ca pf1 capf0 - r/w r/w r/w - r/w r/w r/w address: 92h reset value: 0000 0000b bit name description 6 capen2 input capture 2 enable 0 = input capture channel 2 disable d . 1 = input capture channel 2 enable d . 5 capen1 input capture 1 enable 0 = input capture channel 1 disable d . 1 = input capture channel 1 enable d . 4 capen0 input capture 0 enable 0 = input capture channel 0 disable d . 1 = input capture channel 0 enable d . 2 capf2 input capture 2 flag this bit is set by hardware if the determined edge of input capture 2 occurs. this bit should cleared by software. 1 capf1 input capture 1 flag this bit is set by hardware if the determined edge of input capture 1 occurs. this bit should cleared by software. 0 capf0 input capture 0 flag this bit is set by hardwar e if the determined edge of input capture 0 occurs. this bit should cleared by software.
N76E003 datasheet jun 26 , 201 7 page 31 of 267 rev. 1.02 capcon1 C input capture control 1 7 6 5 4 3 2 1 0 - - cap2ls[1:0] cap1ls[1:0] cap0ls[1:0] - - r/w r/w r/w address: 93h reset value: 0000 0000b bit name description 5:4 cap2ls[1:0] input capture 2 level select 00 = falling edge. 01 = rising edge. 10 = either rising or falling edge. 11 = reserved. 3:2 cap1ls[1:0] input capture 1 level select 00 = falling edge. 01 = rising edge. 10 = either rising or falling edge. 11 = reserved. 1:0 cap0ls[1:0] input capture 0 level select 00 = falling edge. 01 = rising edge. 10 = either rising or falling edge. 11 = reserved. capcon2 C input capture control 2 7 6 5 4 3 2 1 0 - enf2 enf1 enf0 - - - - - r/w r/w r/w - - - - address: 94h reset value: 0000 0000b bit name description 6 enf2 enable noise filer on input capture 2 0 = n oise filter on input capture channel 2 disable d . 1 = n oise filter on input capture channel 2 enable d . 5 enf1 enable noise filer on input capture 1 0 = n oi se filter on input capture channel 1 disable d . 1 = n oise filter on input capture channel 1 enable d . 4 enf0 enable noise filer on input capture 0 0 = n oise filter on input capture channel 0 disable d . 1 = n oise filter on input capture channel 0 enable d .
N76E003 datasheet jun 26 , 201 7 page 32 of 267 rev. 1.02 ck div C clock divider 7 6 5 4 3 2 1 0 ckdiv[7:0] r/w address: 95h reset value: 0000 0000b bit name description 7:0 ckdiv[7:0] clock divider the system clock frequency f sys follows the equation below according to ckdiv value. , while ckdiv = 00h, and , while ckdiv = 01h to ffh. ckswt C clock switch ( ta protected ) 7 6 5 4 3 2 1 0 - - hircst lircst eclkst osc[1:0] - - - r r r w - address: 96h reset value: 0011 0000b bit name description 7 - reserved 6 - reser ved 5 hircst high - speed internal oscillator 16 mhz status 0 = high - speed internal oscillator is not stable or disabled. 1 = high - speed internal oscillator is enabled and stable. - - reserved 3 eclkst external clock input status 0 = external clock input is not stable or disabled. 1 = external clock input is enabled and stable. 2:1 osc[1:0] oscillator selection bits this field select s the system clock source . 00 = internal 16 mhz oscillator. 01 = external clock source according to exten[1:0] (cken[7:6]) s etting. 10 = internal 10 khz oscillator. 11 = reserved. note that this field is write only. the read back value of this field may not correspond to the present system clock source. osc sys f = f ckdiv 2 f = f osc sys
N76E003 datasheet jun 26 , 201 7 page 33 of 267 rev. 1.02 cken C clock enable ( ta protected ) 7 6 5 4 3 2 1 0 exten[1:0] hircen - - - - ckswtf r/w r/w - - - - r address: 97h reset value: 0011 0000b bit name description 7:6 exten[1:0] external clock source enable 11 = external clock input v ia x in enabled. others = external clock input is disable . p 30 work as general purpose i/o. 5 h ircen high - speed internal oscillator 16 mhz enable 0 = the high - speed internal oscillator disabled . 1 = the high - speed internal oscillator enabled. note that once iap is enabled by setting iapen (chpcon.0), the high - speed internal 16 mhz oscillator will be enabled automatically. the hardware will also set hircen and hircst bits. after iapen is cleared, hircen and ehrcst resume the original values. 4 :1 - reserved 0 ckswtf clock switch fault flag 0 = the previous system clock source switch was successful. 1 = user tried to switch to an instable or disabled clock source at the previous system clock source switch. if switching to an instable clock source, this bit remains 1 until the clock source is stable and switching is successful. scon C serial port contr ol (bit - addressable) 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri r/w r/w r/w r/w r/w r/w r/w r/w address: 98h reset value: 0000 0000b bit name description 7 sm0/fe serial port mode select smod0 (pcon.6) = 0: see table 13 - 1 . serial port 0 mode description for details. smod0 (pcon.6) = 1: sm0/fe bit is used as frame error (fe) status flag. it is cleared by software. 0 = frame error (fe) did not occur. 1 = frame error (fe) occurred and detected. 6 sm1
N76E003 datasheet jun 26 , 201 7 page 34 of 267 rev. 1.02 bit name description 5 s m2 multiprocessor communication mode enable the function of this bit is dependent on the serial port 0 mode. mode 0: this bit select the baud rate between f sys /12 and f sys /2. 0 = the clock runs at f sys /12 baud rate. it maintains standard 8051 compatibil ity. 1 = the clock runs at f sys /2 baud rate for faster serial communica - tion. mode 1: this bit checks valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is valid only when the received stop bit is logic 1 and the received data matches given or broadcast address. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9 th bit. 1 = reception is valid only when the received 9 th bit is logic 1 and the received data matches given or broadcast address. 4 ren receiving enable 0 = serial port 0 reception d isabled. 1 = serial port 0 reception e nabled in mode 1,2, or 3. in mode 0, reception is initiated by the condition ren = 1 and ri = 0. 3 tb8 9 th transmitted bit this bit defines the state of the 9 th transmission bit in serial port 0 mode 2 or 3. it is not used in mode 0 or 1. 2 rb8 9 th received bit the bit identifies the logic level of the 9 th received bit in serial port 0 mode 2 or 3. in mode 1, rb8 is the logic level of the received stop bit. sm2 bit as logic 1 has restriction for exception. rb8 is not used in mode 0. 1 ti transmission interrupt flag this flag is set by hardware when a data frame has been transmitted by the serial port 0 af ter the 8 th bit in mode 0 or the last data bit in other modes. when the serial port 0 interrupt is enabled, setting this bit causes the cpu to execute the serial port 0 interrupt service routine. this bit should be cleared manually via software. 0 ri rece iving interrupt flag this flag is set via hardware when a data frame has been received by the serial port 0 after the 8 th bit in mode 0 or after sampling the stop bit in mode 1, 2, or 3. sm2 bit as logic 1 has restriction for exception. when the serial por t 0 interrupt is enabled, setting this bit causes the cpu to execute to the serial port 0 interrupt service routine. this bit should be cleared manually via software.
N76E003 datasheet jun 26 , 201 7 page 35 of 267 rev. 1.02 sbuf C serial port 0 data buffer 7 6 5 4 3 2 1 0 sbuf[7:0] r/w address: 99h reset val ue: 0000 0000b bit name description 7:0 sbuf[7:0] serial port 0 data buffer this byte actually consists two separate registers. one is the receiving resister, and the other is the transmitting buffer. when data is moved to sbuf, it goes to the transmittin g buffer and is shifted for serial transmission. when data is moved from sbuf, it comes from the receiving register. the transmission is initiated through giving data to sbuf. sbuf_1 C serial port 1 data buffer 7 6 5 4 3 2 1 0 sbuf _ 1[7:0] r/w address: 9ah reset value: 0000 0000b bit name description 7:0 sbuf _ 1[7:0] serial port 1 data buffer this byte actually consists two separate registers. one is the receiving resister, and the other is the transmitting buffer. when data is moved to sbuf _1 , it goes t o the transmitting buffer and is shifted for serial transmission. when data is moved from sbuf _1 , it comes from the receiving register. the transmission is initiated through giving data to sbuf _1 . eie C extensive interrupt enable 7 6 5 4 3 2 1 0 et2 espi efb ewdt epwm ecap epi ei2c r/w r/w r/w r/w r/w r/w r/w r/w address: 9bh reset value: 0000 0000b bit name description 7 et2 enable timer 2 interrupt 0 = timer 2 interrupt disable d . 1 = interrupt generated by tf2 (t2con.7) enable d . 6 espi enable spi in terrupt 0 = spi interrupt disable d . 1 = interrupt generated by spif (spsr.7), spiovf (spsr.5), or modf (spsr.4) enable. 5 efb enable fault brake interrupt 0 = fault brake interrupt disable d . 1 = interrupt generated by fbf (fbd.7) enable d. 4 ewdt enable w dt interrupt 0 = wdt interrupt disable d . 1 = interrupt generated by wdtf ( wdcon.5 ) enable d .
N76E003 datasheet jun 26 , 201 7 page 36 of 267 rev. 1.02 bit name description 3 epwm enable pwm interrupt 0 = pwm interrupt disable d . 1 = interrupt generated by pwmf ( pwmcon0.5 ) enable d . 2 ecap enable input capture interrupt 0 = i nput captu re interrupt disable d . 1 = interrupt generated by any flags of capf[2:0] ( capcon0[2:0] ) enable d . 1 epi enable pin interrupt 0 = p in interrupt disable d . 1 = interrupt generated by any flags in pif register enable d . 0 ei2c enable i 2 c interrupt 0 = i 2 c inte rrupt disable d . 1 = interrupt generated by si ( i2con.3 ) or i2tof ( i2toc.0) enable d . eie1 C extensive interrupt enable 1 7 6 5 4 3 2 1 0 - - - - - ewkt et3 es _ 1 - - - - - r/w r/w r/w address: 9ch reset value: 0000 0000b bit name description 2 ewkt enab le wkt interrupt 0 = wkt interrupt disable d . 1 = interrupt generated by wktf (wkcon.4) enable d . 1 et3 enable timer 3 interrupt 0 = timer 3 interrupt disable d . 1 = interrupt generated by tf3 (t3con.4) enable d . 0 es_1 enable serial port 1 interrupt 0 = ser ial port 1 interrupt disable d . 1 = interrupt generated by ti_1 ( scon_1.1 ) or ri_1 ( scon_1.0) enable d . chpcon C chip control ( ta protected ) 7 6 5 4 3 2 1 0 swrst iapff - - - - bs iapen w r/w - - - - r/w r/w address: 9fh reset value: see table 6 - 2 . sfr definitions and reset values bit name description 6 iapff i a p fault flag the hardware will set this bit after iapgo (isptrg.0) is set if any of the following condition is met: ( 1 ) the accessing address is oversize . ( 2 ) iapcn command is invalid. (3) iap erases or programs updating un - enabled block. (4) iap erasing or programming operates under v bod while boi a p (config2.5) remains un - programmed 1 with boden (bodcon0.7) as 1 and borst ( bodcon0 . 2 ) as 0. this bit should be cleared via software. 0 iapen i a p enable
N76E003 datasheet jun 26 , 201 7 page 37 of 267 rev. 1.02 bit name description 0 = iap function disable d . 1 = iap function enable d . once enabl ing i a p function , the hirc will be turned on for timing control. to clear i a pen should always be the last instruction after i a p operation to stop in ternal oscillator if reducing power consumption is concerned . 1 bs boot select this bit defines from which block that mcu re - boots after all resets . 0 = mcu will re - boot from aprom after all resets . 1 = mcu will re - boot from ldrom after all resets . 0 iap en i a p enable 0 = iap function disable d . 1 = iap function enable d . once enabl ing i a p function , the hirc will be turned on for timing control. to clear i a pen should always be the last instruction after i a p operation to stop internal oscillator if reducing p ower consumption is concerned . p2 C port 2 (bit - addressable) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 p2.0 r r r r r r r r address: a0h reset value: 0000 000x b bit name description 7:1 0 reserved the bits are always read as 0. 0 p2 . 0 port 2 bit 0 p2.0 is an inp ut - only pin when rpd (config0.2) is programmed as 0. when leaving rpd un - programmed, p2.0 is always read as 0. auxr1 C auxiliary register 1 7 6 5 4 3 2 1 0 swrf rstpinf hardf - gf2 uart0px 0 dps r/w r/w r/w - r/w r/w r r/w address: a2h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7 swrf software reset flag when the mcu is reset via software reset, this bit will be set via hardware. it is recommended that the flag be cleared via software. 6 rstpinf external reset flag when the mcu is reset by the external reset pin , this bit will be set via hardware. it is recommended that the flag be cleared via software. 5 hardf hard fault reset flag once program counter (pc) is over flash size , mcu will be reset and this bit will be set via hardware. it is recommended that the flag be cleared via software. note: if mcu run in ocd debug mode and ocden = 0, hard fault reset will be disable d and o nly hardf flag be asserted .
N76E003 datasheet jun 26 , 201 7 page 38 of 267 rev. 1.02 bit name description 3 gf2 general p urpose flag 2 the general purpose flag that can be set or cleared by the user via software. 2 uart0px serial port 0 pin exchange 0 = assign rxd to p0 .7 and txd to p0. 6 by default. 1 = exchange rxd to p0. 6 and txd to p 0 . 7 . note that txd and rxd will exchan ge immediately once setting or clearing this bit. user should take care of not exchanging pins during transmission or receiving. or it may cause unpredictable situation and no warning alarms. 1 0 reserved this bit is always read as 0. 0 dps data pointer select 0 = data pointer 0 (dptr) is active by default. 1 = data pointer 1 (dptr1) is active. after dps switches the activated data pointer, the previous inactivated data pointer remains its original value unchanged. bodcon0 C brown - out detection control 0 ( ta protected ) 7 6 5 4 3 2 1 0 boden [1] bov[1:0] [1] bof [ 2 ] borst [1] borf bos r/w r/w r/w r/w r/w r address: a3h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7 boden brown - out detection enable 0 = b rown - out detection circuit off . 1 = b rown - out detection circuit on . note that bod output is not available until 2~3 lirc clocks after enabling. 6:4 bov[1:0] brown - out voltage select 11 = v bod is 2.2 v. 10 = v bod is 2.7 v. 01 = v bo d is 3. 7 v. 00 = v bod is 4.4 v. 3 bof brown - out interrupt flag this flag will be set as logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod (eie.2) and ea (ie.7) are set, a brown - out interrupt requirement will be generated. this bit should be cleared via software. 2 borst brown - out reset enable this bit decides whether a brown - out reset is caused by a power drop below v bod . 0 = brown - out reset when v dd drops below v bod disabled. 1 = brown - out reset when v dd drops below v bod enabled. 1 borf brown - out reset flag when the mcu is reset by brown - out event, this bit will be set via hardware. this flag is recommended to be cleared via software. 0 bos brown - out status this bit indicates the v dd voltage level comparing wi th v bod while bod circuit is enabled. it keeps 0 if bod is not enabled. 0 = v dd voltage level is higher than v bod or bod is disabled . 1 = v dd voltage level is lower than v bod . note that t his bit is read - only . [1] boden, bov[1:0] , and borst are initialized by being directly loaded from config 2 bit 7, [6:4], and 2 after all resets.
N76E003 datasheet jun 26 , 201 7 page 39 of 267 rev. 1.02 [2] bof reset value depends on different setting of config2 and v dd voltage level. please check table 24 - 1 . iaptrg C iap trigger ( ta prot ected ) 7 6 5 4 3 2 1 0 - - - - - - - iapgo - - - - - - - w address: a4h reset value: 0000 0000b bit name description 0 iapgo i a p go iap begins by setting this bit as logic 1. after this instruction, the cpu holds the program counter (pc) and the iap ha rdware automation takes over to control the progress. after iap action completed, the program counter continues to run the following instruction. the iapgo bit will be automatically cleared and always read as logic 0. before triggering an iap action, inter rupts (if enabled) should be temporary di sabled for hardware limitation. iapuen C iap updating enable ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - cfuen lduen apuen - - - - - r/w r/w r/w address: a5h reset value: 0000 0000b bit name description 2 cfuen co nfig bytes updated enable 0 = inhibit erasing or programming config bytes by iap. 1 = allow erasing or programming config bytes by iap. 1 lduen ldrom updated enable 0 = inhibit erasing or programming ldrom by iap. 1 = allow erasing or programming ldrom by iap. 0 apuen aprom updated enable 0 = inhibit erasing or programming aprom by iap. 1 = allow erasing or programming aprom by iap. iapal C iap address low byte 7 6 5 4 3 2 1 0 iapa[7:0] r/w address: a6h reset value: 0000 0000b bit name description 7: 0 iapa[7:0] iap address low byte iapal contains address iapa[7:0] for iap operations.
N76E003 datasheet jun 26 , 201 7 page 40 of 267 rev. 1.02 iapah C iap address high byte 7 6 5 4 3 2 1 0 iapa[15:8] r/w address: a7h reset value: 0000 0000b bit name description 7:0 iapa[15:8] iap address high byte iapah con tains address iapa[15:8] for iap operations. ie C interrupt enable (bit - addressable) 7 6 5 4 3 2 1 0 ea eadc ebod es et1 ex1 et0 ex0 r/w r/w r/w r/w r/w r/w r/w r/w address: a8h reset value: 0000 0000b bit name description 7 ea enable all interrupt th is bit globally enables/disables all interrupts that are individually enabled. 0 = a ll interrupt sources disable d . 1 = e ach interrupt enable d depending on its individual mask setting. individual interrupts will occur if enabled. 6 eadc enable adc interrup t 0 = adc interrupt disable d . 1 = interrupt generated by adcf ( adccon0.7 ) enable d . 5 ebod enable brown - out interrupt 0 = brown - out detection interrupt disable d . 1 = interrupt generated by bof ( bodcon0.3 ) enable d . 4 es enable serial port 0 interrupt 0 = s erial port 0 interrupt disable d . 1 = interrupt generated by ti ( scon.1 ) or ri ( scon.0) enable d . 3 et1 enable timer 1 interrupt 0 = timer 1 interrupt disable d . 1 = interrupt generated by tf1 ( tcon.7 ) enable d . 2 ex1 enable external interrupt 1 0 = external interrupt 1 disable d . 1 = interrupt generated by ? ? ? ? ? ? ? pin (p 1 . 7 ) enable d . 1 et0 enable timer 0 interrupt 0 = timer 0 interrupt disable d . 1 = interrupt generated by tf0 ( tcon.5 ) enable d . 0 ex0 enable external interrupt 0 0 = external interrupt 0 disabl e d . 1 = interrupt generated by ? ? ? ? ? ? ? pin ( p 3 .0) enable d .
N76E003 datasheet jun 26 , 201 7 page 41 of 267 rev. 1.02 saddr C slave 0 address 7 6 5 4 3 2 1 0 saddr[7:0] r/w address: a9h reset value: 0000 0000b bit name description 7:0 saddr[7:0] slave 0 address his byte specifies the microcontrollers own sla ve address for uatr0 multi - processor communication. wdcon C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 wdt r wdclr wdtf widpd wdtrf wdps[2:0] r/w r/w r/w r/w r/w r/w address: aah reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7 wdtr wdt run this bit is valid only when control bits in wdten[3:0] (config4[7:4]) are all 1. at this time, wdt works as a general purpose timer. 0 = wdt disable d . 1 = wdt enabled. the wdt cou nter starts running. 6 wdclr wdt clear setting this bit will reset the wdt count to 00h. it puts the counter in a known state and prohibit the system from unpredictable reset. the meaning of writing and reading wdclr bit is different. writing: 0 = no eff ect. 1 = clearing wdt counter. reading: 0 = wdt counter is completely cleared. 1 = wdt counter is not yet cleared. 5 wdtf wdt time - out flag this bit indicates an overflow of wdt counter. this flag should be cleared by software. 4 widpd wdt running in idle or power - down mode this bit is valid only when control bits in wdten[3:0] (config4[7:4]) are all 1. it decides whether wdt runs in idle or power - down mode when wdt works as a general purpose timer. 0 = wdt stops running during idle or power - down mode. 1 = wdt keeps running during idle or power - down mode. 3 wdtrf wdt reset flag when the mcu is reset by wdt time - out event, this bit will be set via hardware. it is recommended that the flag be cleared via software. 2:0 wdps[2:0] wdt clock pre - scalar sele ct these bits determine the pre - scale of wdt clock from 1/1 through 1/256. see table 11 - 1 . the default is the maximum pre - scale value. [1] wdtrf will be cleared after power - on reset, be set after wdt reset, and re mains unchanged after any other resets. [2] wdps[2:0] are all set after power - on reset and keep unchanged after any reset other than power - on reset.
N76E003 datasheet jun 26 , 201 7 page 42 of 267 rev. 1.02 bodcon1 C brown - out detection control 1 ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - lpbod[1:0] bodflt - - - - - r/w r/w address: abh reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7:3 - reserved 2:1 lpbod[1:0] low power bod enable 00 = bod n ormal mod e . bod circuit is always enabled. 01 = bod l ow power mode 1 by turning on bod circuit every 1.6 ms periodically. 10 = bod l ow power mode 2 by turning on bod circuit every 6.4 ms periodically. 11 = bod l ow power mode 3 by turning on bod circuit every 25.6 ms periodically. 0 bodflt bod filt er control bod has a filter which counts 32 clocks of f sys to filter the power noise when mcu runs with hirc, or eclk as the system clock and bod does not operates in its low power mode (lpbod[1:0] = [0, 0]). in other conditions, the filter counts 2 clocks of lirc. note that when cpu is halted in power - down mode. the bod output is permanently filtered by 2 clocks of lirc. the bod filter avoids the power noise to trigger bod event. this bit controls bod filter enabled or disabled. 0 = bod filter disabled. 1 = bod filter enabled. (power - on reset default value.)
N76E003 datasheet jun 26 , 201 7 page 43 of 267 rev. 1.02 p3m1 C port 3 mode select 1 7 6 5 4 3 2 1 0 - - - - - - - p3m1.0 [ 3 ] - - - - - - - r/w address: ach, page: 0 reset value: 0000 000 1b bit name description 0 p3m1 . 0 port 3 mode select 1 [ 3 ] p3m1 an d p3m2 are used in combination to determine the i/o mode of each pin of p3. see table 7 - 1 . configuration for different i/o modes . p3s C port 3 schmitt triggered input 7 6 5 4 3 2 1 0 - - - - - - - p3s.0 - - - - - - - r/w address: ach, page: 1 reset value: 0000 0000b bit name description 0 p3s. 0 p3. 0 schmitt triggered input 0 = ttl level input of p3. 0 . 1 = schmitt triggered input of p3. 0 . p3m2 C port 3 mode select 2 7 6 5 4 3 2 1 0 - - - - - - - p3m2.0 [ 3 ] - - - - - - - r/w address: adh, page: 0 reset value: 0000 0000b bit name description 0 p3m2 . 0 port 3 mode select 2 [ 3 ] p3m1 and p3m2 are used in combination to determine the i/o mode of each pin of p3. see table 7 - 1 . configuration for different i/o modes . p3sr C port 3 slew rate 7 6 5 4 3 2 1 0 - - - - - - - p3sr.0 - - - - - - - r/w address: adh, page: 1 reset value: 0000 0000b bit name description 0 p3sr. 0 p3.n slew rate 0 = p3. 0 normal output slew rate. 1 = p3. 0 high - speed output slew rate.
N76E003 datasheet jun 26 , 201 7 page 44 of 267 rev. 1.02 iapfd C iap flash data 7 6 5 4 3 2 1 0 iapfd[7:0] r/w address: aeh reset value: 0000 0000b bit name description 7:0 iapfd[7:0] iap flash data this byte contains flash data, which is read from or is going to be written to the flash memory. user should write data into iapfd for program mode before triggering iap processing and read data from iapfd for read/verify mode after iap processing is finished. iapcn C iap control 7 6 5 4 3 2 1 0 iapb[1:0] foen fcen fctrl[3:0] r/w r/w r/w r/w address: afh reset value: 0011 0000b bit name description 7:6 iapb[1:0] i a p control this byte is used for i a p command. for details, see table 21 - 1 . iap modes and command codes . 5 foen 4 fcen 3:0 fctrl[3:0] p3 C port 3 (bit - addressable) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 p3.0 r r r r r r r r/w address: b0h reset value: 0000 0001b bit name description 7:1 0 reserved the bits are always read as 0. 0 p3.0 port 3 bit 0 p 3.0 is available only when th e internal oscillator is used as the system clock. at this moment, p3.0 functions as a general purpose i/o. if the system clock is not selected as the internal oscillator , p3.0 pin functions as oscin. a write to p3.0 is invalid and p3.0 is always read as 0 .
N76E003 datasheet jun 26 , 201 7 page 45 of 267 rev. 1.02 p0m1 C port 0 mode select 1 [ 1 ] 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b1h, page: 0 reset value: 1111 1111b bit name description 7:0 p0m1[7:0] port 0 mode select 1 [1] p0m1 an d p0m2 are used in combination to determine the i/o mode of each pin of p0. see table 7 - 1 . configuration for different i/o modes . p 0 m1.n p 0 m2.n i/o type 0 0 quasi - bidirectional 0 1 push - pull 1 0 input - only (high - impedance) 1 1 open - drain p0s C port 0 schmitt triggered input 7 6 5 4 3 2 1 0 p0s.7 p0s.6 p0s.5 p0s.4 p0s.3 p0s.2 p0s.1 p0s.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b1h, page: 1 reset value: 0000 0000b bit name description n p0s.n p0.n schmitt t riggered input 0 = ttl level input of p0.n. 1 = schmitt triggered input of p0.n. p0m2 C port 0 mode select 2 [ 1 ] 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2.5 p0m2.4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b2h, page: 0 reset value: 0 000 0000b bit name description 7:0 p0m2[7:0] port 0 mode select 2 [1] p0m1 and p0m2 are used in combination to determine the i/o mode of each pin of p0. see table 7 - 1 . configuration for different i/o modes .
N76E003 datasheet jun 26 , 201 7 page 46 of 267 rev. 1.02 p0sr C port 0 slew rate 7 6 5 4 3 2 1 0 p0sr.7 p0sr.6 p0sr.5 p0sr.4 p0sr.3 p0sr.2 p0sr.1 p0sr.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b2h, page: 1 reset value: 0000 0000b bit name description n p0sr.n p0.n slew rate 0 = p0.n normal output slew rate. 1 = p0.n high - speed output slew rate. p1m1 C port 1 mode select 1 [ 2 ] 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b3h, page: 0 reset value: 1111 11 11b bit name description 7 :0 p 1 m1[ 7 :0] port 1 mode select 1 [2] p1m1 and p1m2 are used in combination to determine the i/o mode of each pin of p1. see table 7 - 1 . configuration for different i/o modes . p 1 s C port 1 schmitt triggered input 7 6 5 4 3 2 1 0 p 1 s.7 p 1 s.6 p 1 s.5 p 1 s.4 p 1 s.3 p 1 s.2 p 1 s.1 p 1 s.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b 3 h, page: 1 reset value: 0000 0000b bit name description n p 1 s.n p 1 .n schmitt triggered input 0 = ttl level input of p 1 .n. 1 = schmitt triggered input of p 1 .n. p1m2 C port 1 mode select 2 [ 2 ] 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 p1m2.5 p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b4h, page: 0 reset value: 0000 0000b bit name description 7 :0 p 1 m2[ 7 :0] port 1 mode select 2. [2] p1m1 and p1m2 are used in combination to determine the i/o mode of each pin of p1. see table 7 - 1 . configuration for different i/o modes .
N76E003 datasheet jun 26 , 201 7 page 47 of 267 rev. 1.02 p1sr C port 1 slew rate 7 6 5 4 3 2 1 0 p1sr.7 p1sr.6 p1sr.5 p1sr.4 p1sr.3 p1sr.2 p1 sr.1 p1sr.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b4h, page: 1 reset value: 0000 0000b bit name description n p1sr.n p1.n slew rate 0 = p1.n normal output slew rate. 1 = p1.n high - speed output slew rate. p2s C p 20 s etting and timer01 output enable 7 6 5 4 3 2 1 0 p20 up - - - t1oe t0oe - p2s.0 r/w - - - r/w r/w - r/w address: b5h reset value: 0000 0000b bit name description 7 p20 up p2.0 pull - up enable 0 = p2.0 pull - up disabled. 1 = p2.0 pull - up enabled. this bit is valid only when rpd (config0.2) is programmed as 0. when selecting as a ? ? ? ? ? ? pin, the pull - up is always enabled. 3 t1oe timer 1 output enable 0 = timer 1 output disabled. 1 = timer 1 output enabled from t1 pin. ote that imer output should be enabled only when operating in its ime r mode. 2 t0oe timer 0 output enable 0 = timer 0 output disabled. 1 = timer 0 output enabled from t0 pin. ote that imer output should be enabled only when operating in its imer mode. 0 p2s. 0 p2. 0 schmitt triggered input 0 = ttl level input of p2. 0 . 1 = schmitt triggered input of p2. 0 . iph C interrupt priority high [2] 7 6 5 4 3 2 1 0 - padch pbodh psh pt1h px1h pt0h px0h - r/w r/w r/w r/w r/w r/w r/w address: b7h , page0 reset value: 0000 0000b bit name description 6 padc adc interrupt priority high bit 5 pbod brown - out detection interrupt priority high bit 4 psh serial port 0 interrupt priority high bit 3 pt1h timer 1 interrupt priority high bit
N76E003 datasheet jun 26 , 201 7 page 48 of 267 rev. 1.02 bit name description 2 px1h external interrupt 1 priority high bit 1 pt0h timer 0 interrupt priority high bit 0 px0 h external interrupt 0 priority high bit [2] iph is used in combination with the ip respectively to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct int errupt priority configuration. pwm intc C pwm interrupt control 7 6 5 4 3 2 1 0 - - inttyp1 inttyp0 - intsel 2 intsel1 intsel0 - - r/w r/w - r/w r/w r/w address: b7 h , page:1 reset value: 0000 0000b bit name description 5 : 4 inttyp[1:0] pwm interrupt type select these bit select pwm interrupt type. 00 = falling edge on pwm0 /1 /2 /3 /4 /5 pin. 01 = rising edge on pwm0 /1 /2 /3 /4 /5 pin. 10 = central point of a pwm period. 11 = end point of a pwm period. note that the central point interrupt or the end point interrup t is only available while pwm operates in center - aligned type. 2 :0 intsel[ 2 :0] pwm interrupt pair select these bits select which pwm channel asserts pwm interrupt when pwm interrupt type is selected as falling or rising edge on pwm0/ 1/ 2/ 3/ 4 /5 pin.. 0 00 = pwm0. 0 01 = pwm 1 . 0 10 = pwm 2 . 011 = pwm3. 100 = pwm4. 101 = pwm5. o thers = pwm0. ip C interrupt priority (bit - addressable) [1] 7 6 5 4 3 2 1 0 - padc pbod ps pt1 px1 pt0 px0 - r/w r/w r/w r/w r/w r/w r/w address: b8h reset value: 0000 0000b bit name des cription 6 padc adc interrupt priority low bit 5 pbod brown - out detection interrupt priority low bit 4 ps serial port 0 interrupt priority low bit 3 pt1 timer 1 interrupt priority low bit 2 px1 external interrupt 1 priority low bit 1 pt0 timer 0 inte rrupt priority low bit 0 px0 external interrupt 0 priority low bit
N76E003 datasheet jun 26 , 201 7 page 49 of 267 rev. 1.02 [1] ip is used in combination with the iph to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting f or correct interrupt priority configuration. saden C slave 0 address mask 7 6 5 4 3 2 1 0 saden[7:0] r/w address: b9h reset value: 0000 0000b bit name description 7:0 saden[7:0] slave 0 address mask this byte is a mask byte of uart0 that contains don t - care bits (defined by zeros) to form the devices given address. the dont - care bits provide the flexibility to address one or more slaves at a time. saden_1 C slave 1 address mask 7 6 5 4 3 2 1 0 saden _ 1[7:0] r/w address: bah reset value: 0000 0 000b bit name description 7:0 saden _ 1[7:0] slave 1 address mask this byte is a mask byte of uart1 that contains dont - care bits (defined by zeros) to form the devices given address. the dont - care bits provide the flexibility to address one or more s laves at a time. saddr_1 C slave 1 address 7 6 5 4 3 2 1 0 saddr _ 1[7:0] r/w address: bbh reset value: 0000 0000b bit name description 7:0 saddr _ 1[7:0] slave 1 address his byte specifies the microcontrollers own slave address for uart1 multi - processo r communication.
N76E003 datasheet jun 26 , 201 7 page 50 of 267 rev. 1.02 i2dat C i 2 c data 7 6 5 4 3 2 1 0 i2dat[7:0] r/w address: bch reset value: 0000 0000b bit name description 7 :0 i2dat[7:0] i 2 c data i2dat contains a byte of the i 2 c data to be transmitted or a byte, which has just received. data in i2da t remains as long as si is logic 1. the result of reading or writing i2dat during i 2 c transceiving progress is unpredicted. while data in i2dat is shifted out, data on the bus is simultaneously being shifted in to update i2dat. i2dat always shows the last byte that presented on the i 2 c bus. thus the event of lost arbitration, the original value of i2dat changes after the transaction. i2stat C i 2 c status 7 6 5 4 3 2 1 0 i2stat[7:3] 0 0 0 r r r r address: bdh reset value: 1111 1000b bit name description 7 :3 i2stat[7:3] i 2 c status code the msb five bits of i2stat contains the status code. there are 2 7 possible status codes. when i2stat is f8h, no relevant state information is available and si flag keeps 0. all other 2 6 status codes correspond to the i 2 c st ates. when each of these status is entered, si will be set as logic 1 and a interrupt is requested. 2:0 0 reserved the least significant three bits of i2stat are always read as 0.
N76E003 datasheet jun 26 , 201 7 page 51 of 267 rev. 1.02 i2clk C i 2 c clock 7 6 5 4 3 2 1 0 i2clk[7:0] r/w address: beh reset val ue: 0000 10 01 b bit name description 7:0 i2clk[7:0] i 2 c clock setting in master mode: this register determines the clock rate of i 2 c bus when the device is in a master mode. the clock rate follows the equation, . the default value wil l make the clock rate of i 2 c bus 400k bps if the peripheral clock is 16 mhz. note that the i2clk value of 00h and 01h are not valid. this is an implement limitation. in slave mode: this byte has no effect. in slave mode, the i 2 c device will automatically s ynchronize with any given clock rate up to 400k b ps. i2toc C i 2 c time - out counter 7 6 5 4 3 2 1 0 - - - - - i2tocen div i2tof - - - - - r/w r/w r/w address: bfh reset value: 0000 0000b bit name description 2 i2tocen i 2 c time - out counter enable 0 = i 2 c time - out counter d isabled. 1 = i 2 c time - out counter e nabled. 1 div i 2 c time - out counter clock divider 0 = the clock of i 2 c time - out counter is f sys /1 . 1 = the clock of i 2 c time - out counter is f sys /4 . 0 i2tof i 2 c time - out flag this flag is set by hardwar e if 14 - bit i 2 c time - out counter overflows. it is cleared by software. ) 1 + clk 2 i ( 4 f sys
N76E003 datasheet jun 26 , 201 7 page 52 of 267 rev. 1.02 i2con C i 2 c control (bit - addressable) 7 6 5 4 3 2 1 0 - i2cen sta sto si aa - i2c px - r/w r/w r/w r/w r/w - r/w address: c0h reset value: 0000 0000b bit name description 6 i2cen i 2 c bus enable 0 = i 2 c bus d isabled. 1 = i 2 c bus e nabled. before enabling the i 2 c, scl and sda port latches should be set to logic 1. 5 sta start flag when sta is set, the i 2 c generates a start condition if the bus is free. if the bus is busy, the i 2 c waits for a stop condition and generates a start condition following. if sta is set while the i 2 c is already in the master mode and one or more bytes have been transmitted or received, the i 2 c generates a repeated start condition. note that sta can be set anyti me even in a slave mode, but sta is not hardware automatically cleared after start or repeated start condition has been detected. user should take care of it by clearing sta manually. 4 sto stop flag when sto is set if the i 2 c is in the master mode, a sto p condition is transmitted to the bus. sto is automatically cleared by hardware once the stop condition has been detected on the bus. the sto flag setting is also used to recover the i 2 c device from the bus error state (i2stat as 00h). in this case, no sto p condition is transmitted to the i 2 c bus. if the sta and sto bits are both set and the device is original in the master mode, the i 2 c bus will generate a stop condition and immediately follow a start condition. if the device is in slave mode, sta and sto simultaneous setting should be avoid from issuing illegal i 2 c frames. 3 si i 2 c interrupt flag si flag is set by hardware when one of 2 6 possible i 2 c status (besides f8h status) is entered. after si is set, the software should read i2stat register to deter mine which step has been passed and take actions for next step. si is cleared by software. before the si is cleared, the low period of scl line is stretched. the transaction is suspended. it is useful for the slave device to deal with previous data bytes u ntil ready for receiving the next byte. the serial transaction is suspended until si is cleared by software. after si is cleared, i 2 c bus will continue to generate start or repeated start condition, stop condition, 8 - bit data, or so on depending on the sof tware configuration of controlling byte or bits. therefore , user should take care of it by preparing suitable setting of registers before si is software cleared.
N76E003 datasheet jun 26 , 201 7 page 53 of 267 rev. 1.02 bit name description 2 aa acknowledge assert flag if the aa flag is set, an ack (low level on sda) will be returne d during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver or an own - address - matching slave. if the aa flag is cleared, a nack (high level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver or an own - address - matching slave . a device with its own aa flag cleared will ignore its own salve address and the general call. consequently, si will note be asserted and no interrupt is requested. note that if an addressed slave doe s not return an ack under slave receiver mode or not receive an ack under slave transmitter mode, the slave device will become a not addressed slave. it cannot receive any data until its aa flag is set and a master addresses it again. there is a special ca se of i2stat value c8h occurs under slave transmitter mode. before the slave device transmit the last data byte to the master, aa flag can be cleared as 0. then after the last data byte transmitted, the slave device will actively switch to not addressed sl ave mode of disconnecting with the master. the further reading by the master will be all ffh. 0 i2c px i2c pin s select 0 = assign scl to p1.3 and s da to p1.4. 1 = assign scl to p0. 2 and s da to p1. 6 . note that i2c pins will exchange immediately once setting or clearing this bit. i2addr C i 2 c own slave address 7 6 5 4 3 2 1 0 i2addr[7:1] gc r/w r/w address: c1h reset value: 0000 0000b bit name description 7:1 i2addr[7:1] i 2 c devices own slave address in master mode: these bits have no effect. in slave m ode: these 7 bits define the slave address of this i 2 c device by user. the master should address i 2 c device by sending the same address in the first byte data after a start or a repeated start condition. if the aa flag is set, this i 2 c device will acknowle dge the master after receiving its own address and become an addressed slave. otherwise, the addressing from the master will be ignored. note that i2addr[7:1] should not remain its default value of all 0, because address 0x00 is reserved for general call. 6 gc general call bit in master mode: this bit has no effect. in slave mode: 0 = the general call is always ignored. 1 = the general call is recognized if aa flag is 1; otherwise, it is ignored if aa is 0.
N76E003 datasheet jun 26 , 201 7 page 54 of 267 rev. 1.02 adcrl C adc result low byte 7 6 5 4 3 2 1 0 - - - - adcr[3:0] - - - - r address: c2h reset value: 0000 0000b bit name description 3:0 adcr[3:0] adc result low byte the least significant 4 bits of the adc result stored in this register. adcrh C adc result high byte 7 6 5 4 3 2 1 0 adcr[11:4] r ad dress: c3h reset value: 0000 0000b bit name description 7:0 adcr[11:4] adc result high byte the most significant 8 bits of the adc result stored in this register. t3con C timer 3 control 7 6 5 4 3 2 1 0 smod _ 1 smod0 _ 1 brck tf3 tr3 t3ps[2:0] r/w r/w r/w r/w r/w r/w address: c4h , page:0 reset value: 0000 0000b bit name description 7 smod _ 1 serial port 1 double baud rate enable setting this bit doubles the serial port baud rate when uart1 is in mode 2. see table 13 - 2 . serial port 1 mode description for details. 6 smod0 _ 1 serial port 1 framing error access enable 0 = scon_1.7 accesses to sm0_1 bit. 1 = scon_1.7 accesses to fe_1 bit. 5 brck serial port 0 baud rate clock source this bit selects which timer is used as the baud rate clock source when serial port 0 is in mode 1 or 3. 0 = timer 1 . 1 = timer 3. 4 tf3 timer 3 overflow flag this bit is set when timer 3 overflows. it is automatically cleared by hardware when the program executes the timer 3 interrupt servi ce routine. this bit can be set or cleared by software. 3 tr3 timer 3 run control 0 = timer 3 is halted. 1 = timer 3 starts running. note that the reload registers rh3 and rl3 can only be written when timer 3 is halted (tr3 bit is 0). if any of rh3 or rl3 is written if tr3 is 1, result is unpredictable.
N76E003 datasheet jun 26 , 201 7 page 55 of 267 rev. 1.02 bit name description 2:0 t3ps[2:0] timer 3 pre - scalar these bits determine the scale of the clock divider for timer 3. 000 = 1/1. 001 = 1/2. 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. pwm4h C pwm4 duty high byte 7 6 5 4 3 2 1 0 pwm4[1 5 :8] r/w address: c4 h , page:1 reset value: 0000 0000b bit name description 7 :0 pwm4[1 5 :8] pwm 4 duty high byte this byte with pwm 4l controls the duty of the output signal p g4 from pwm generator . rl3 C timer 3 reload low byte 7 6 5 4 3 2 1 0 rl3[7:0] r/w address: c5h , page:0 reset value: 0000 0000b bit name description 7:0 rl3[7:0] timer 3 reload low byte i t holds the low byte of the reload value of timer 3 . pwm 5 h C pwm 5 duty high byte 7 6 5 4 3 2 1 0 pwm 5 [15:8] r/w address: c5 h , page:1 reset value: 0000 0000b bit name description 7 :0 pwm 5 [15:8] pwm 5 duty high byte this byte with pwm 5 l controls the duty of the output signal p g 5 from pwm generator .
N76E003 datasheet jun 26 , 201 7 page 56 of 267 rev. 1.02 rh3 C timer 3 reload high byte 7 6 5 4 3 2 1 0 rh3[7:0] r/w address: c6h , page:0 reset value: 0000 0000b bit name description 7:0 rh3[7:0] timer 3 reload high byte i t holds the high byte of the reload value of time 3 . pio con1 C pwm or i/o select 7 6 5 4 3 2 1 0 - - pio 1 5 - pio 1 3 pio 1 2 pio 1 1 - - - r/w - r/w r/w r/w - address: c6 h , page:1 reset value: 0000 0000b bit name description 5 pio 1 5 p 1 . 5 /pwm5 pin function select 0 = p 1 . 5 /pwm5 pin functions as p 1 . 5 . 1 = p 1 . 5 /pwm5 pin functions as pwm5 output. 3 pio 1 3 p0. 4 /pwm3 pin function select 0 = p0. 4 /pwm3 pin funct ions as p0. 4 . 1 = p0. 4 /pwm3 pin functions as pwm3 output. 2 pio 1 2 p 0 . 5 /pwm2 pin function select 0 = p0. 5 /pwm2 pin functions as p0. 5 . 1 = p0. 5 /pwm2 pin functions as pwm2 output. 1 pio 1 1 p1. 4 /pwm1 pin function select 0 = p1. 4 /pwm1 pin functions as p1. 4 . 1 = p1. 4 /pwm1 pin functions as pwm1 output. ta C timed access 7 6 5 4 3 2 1 0 ta[7:0] w address: c7h reset value: 0000 0000b bit name description 7:0 ta[7:0] timed access the timed access register controls the access to protected sfrs. to access protect ed bits, user should first write aah to the ta and immediately followed by a write of 55h to ta. after these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected sfrs.
N76E003 datasheet jun 26 , 201 7 page 57 of 267 rev. 1.02 t2con C timer 2 cont rol 7 6 5 4 3 2 1 0 tf2 - - - - tr2 - ? ? ? ? ? ? r/w - - - - r/w - r/w address: c8h reset value: 0000 0000b bit name description 7 tf2 timer 2 overflow flag this bit is set when timer 2 overflows or a compare match occurs. if the timer 2 interrupt and th e global interrupt are enable, setting this bit will make cpu execute timer 2 interrupt service routine. this bit is not automatically cleared via hardware and should be cleared via software. 2 tr2 timer 2 run control 0 = timer 2 disabled . clearing this b it will halt timer 2 and the current count will be preserved in th2 and tl2. 1 = timer 2 e nabled. 0 ? ? ? ? ? ? timer 2 compare or auto - reload mode select this bit selects timer 2 functioning mode. 0 = auto - reload mode. 1 = compare mode. t2mod C timer 2 mod e 7 6 5 4 3 2 1 0 lden t2div[2:0] capcr cmpcr ldts[1:0] r/w r/w r/w r/w r/w address: c9h reset value: 0000 0000b bit name description 7 lden enable auto - reload 0 = reloading rcmp2h and rcmp2l to th2 and tl2 disable d . 1 = r eloading rcmp2h and rcmp2l to th2 and tl2 en able d. 6:4 t2div[2:0] timer 2 clock divider 0 00 = timer 2 clock divider is 1/1. 0 01 = timer 2 clock divider is 1/4. 0 10 = timer 2 clock divider is 1/16. 0 11 = timer 2 clock divider is 1/32. 100 = timer 2 clock divider is 1/64. 101 = timer 2 clock divider is 1/128. 110 = timer 2 clock divider is 1/256. 111 = timer 2 clock divider is 1/512. 3 capcr capture auto - clear this bit is valid only under timer 2 auto - reload mode. it enables hardware auto - clearing th2 and tl2 counter registers after the y have been transferred in to rcmp2h and rcmp2l while a capture event occurs. 0 = timer 2 continues counting when a capture event occurs. 1 = timer 2 value is auto - cleared as 0000h when a capture event occurs. 2 cmpcr compare match auto - clear this bit is valid only under timer 2 compare mode. it enables hardware auto - clearing th2 and tl2 counter registers after a compare match occurs. 0 = timer 2 continues counting when a compare match occurs. 1 = timer 2 value is auto - cleared as 0000h when a compare match occurs.
N76E003 datasheet jun 26 , 201 7 page 58 of 267 rev. 1.02 bit name description 1:0 ldts[1:0] auto - reload trigger select these bits select the reload trigger event. 00 = reload when timer 2 overflows. 01 = reload when input capture 0 event occurs. 10 = reload when input capture 1 event occurs. 11 = reload when input capture 2 event occurs. rcmp2l C timer 2 reload/compare low byte 7 6 5 4 3 2 1 0 rcmp2l[7:0] r/w address: cah reset value: 0000 0000b bit name description 7:0 rcmp2l[7:0] timer 2 reload/compare low byte th is register stores the low byte of compare value when timer 2 is configured in compare mode. also it holds the low byte of the reload value in auto - reload mode. rcmp2h C timer 2 reload/compare high byte 7 6 5 4 3 2 1 0 rcmp2h[7:0] r/w address: cbh reset value: 0000 0000b bit name description 7:0 rcmp2h[7 :0] timer 2 reload/compare high byte th is register stores the high byte of compare value when timer 2 is configured in compare mode. also it holds the high byte of the reload value in auto - reload mode. tl2 C timer 2 low byte 7 6 5 4 3 2 1 0 tl2[7:0] r/w address: cch , page:0 reset value: 0000 0000b bit name description 7:0 tl2[7:0] timer 2 low byte the tl2 register is the low byte of the 16 - bit counting register of timer 2.
N76E003 datasheet jun 26 , 201 7 page 59 of 267 rev. 1.02 pwm4l C pwm4 duty low byte 7 6 5 4 3 2 1 0 pwm4[7:0] r/w address: cc h , page: 1 reset value: 0000 0000b bit name description 7:0 pwm4[7:0] pwm 4 duty low byte this byte with pwm 4 h controls the duty of the output signal p g4 from pwm generator . th2 C timer 2 high byte 7 6 5 4 3 2 1 0 th2[7:0] r/w address: cdh , page:0 reset value: 0000 0000b bit name description 7:0 th2[7:0] timer 2 high byte the th2 register is the high byte of the 16 - bit counting register of timer 2. pwm 5 l C pwm 5 duty low byte 7 6 5 4 3 2 1 0 pwm 5 [7:0] r/w address: c dh , page:1 reset value: 0000 0000b bit name description 7:0 pwm 5 [7:0] pwm 5 duty low byte this byte with pwm 5 h controls the duty of the output signal p g 5 from pwm generator . adcmpl C adc compare low byte 7 6 5 4 3 2 1 0 - - - - adcmp[3:0] - - - - w/r address: ceh reset value: 0000 0000b bit nam e description 3:0 adcmp[3:0] adc compare low byte the least significant 4 bits of the adc compare value stores in this register.
N76E003 datasheet jun 26 , 201 7 page 60 of 267 rev. 1.02 adcmph C adc compare high byte 7 6 5 4 3 2 1 0 adcmp[11:4] w/r address: cfh reset value: 0000 0000b bit name description 7:0 adcmp[11:4] adc compare high byte the most significant 8 bits of the adc compare value stores in this register. psw C program status word (bit - addressable) 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p r/w r/w r/w r/w r/w r/w r/w r address: d0h reset va lue: 0000 0000b bit name description 7 cy carry flag for a adding or subtracting operation, cy will be set when the previous operation resulted in a carry - out from or a borrow - in to the most significant bit , otherwise cleared. if the previous operation is mul or div, cy is always 0. cy is affected by da a instruction, which indicates that if the original bcd sum is greater than 100. for a cjne branch, cy will be set if the first unsigned integer value is less than the second one. otherwise, cy will be clea red. 6 ac auxiliary carry set when the previous operation resulted in a carry - out from or a borrow - in to the 4th bit of the low order nibble, otherwise cleared. 5 f0 user flag 0 the g eneral purpose flag that can be set or cleared by user. 4 rs1 register b ank selecti on bits these two bits select one of four banks in which r0 to r7 locate. rs1 rs0 register bank ram address 0 0 0 00 h to 07 h 0 1 1 08 h to 0f h 1 0 2 10 h to 17 h 1 1 3 18 h to 1f h 3 rs0 2 ov overflow flag ov is used for a signed character operands. for a add or addc instruction, ov will be set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6. otherwise, ov is cleared. ov indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. for a subb, ov is set if a borrow is needed into bit6 but not into bit 7, or into bit7 but not bit 6. otherwise, ov is cleared. ov indicates a negative number produced when a negative value is subtracted from a po sitive value, or a positive result when a positive number is subtracted from a negative number. for a mul, if the product is greater than 255 ( 0 0ffh), ov will be set. otherwise, it is cleared. for a div, it is normally 0. however, if b had originally conta ined 00h, the values returned in a and b will be undefined. meanwhile, the ov will be set.
N76E003 datasheet jun 26 , 201 7 page 61 of 267 rev. 1.02 bit name description 1 f1 user f lag 1 the g eneral purpose flag that can be set or cleared by user via software. 0 p parity flag set to 1 to indicate an odd number of ones in the accumu lator. cleared for an even number of ones. it performs even parity check. table 6 - 3 . instructions t hat a ffect f lag s ettings instruction cy ov ac instruction cy ov ac add x [1] x x clr c 0 addc x x x cpl c x subb x x x anl c, bit x mul 0 x anl c, /bit x div 0 x orl c, bit x da a x orl c, /bit x rrc a x mov c, bit x rlc a x cjne x setb c 1 [1] x indicates the modification depends on the result of the instruction. pwmph C pw m period high byte 7 6 5 4 3 2 1 0 pwmp[1 5 :8] r/w address: d1h reset value: 0000 0000b bit name description 7 :0 pwmp[1 5 :8] pwm period high byte this byte with pwmpl controls the period of the pwm generator signal. pwm0h C pwm0 duty high byte 7 6 5 4 3 2 1 0 pwm0 [15:8] r/w address: d2h reset value: 0000 0000b bit name description 7 :0 pwm0[1 5 :8] pwm0 duty high byte this byte with pwm0 l controls the duty of the output signal p g 0 from pwm generator .
N76E003 datasheet jun 26 , 201 7 page 62 of 267 rev. 1.02 pwm1h C pwm1 duty high byte 7 6 5 4 3 2 1 0 pwm1 [15 :8] r/w address: d 3 h reset value: 0000 0000b bit name description 7 :0 pwm1 [15:8] pwm 1 duty high byte this byte with pwm 1l controls the duty of the output signal p g1 from pwm generator . pwm2h C pwm2 duty high byte 7 6 5 4 3 2 1 0 pwm2[1 5 :8] r/w addre ss: d 4 h reset value: 0000 0000b bit name description 7 :0 pwm2[1 5 :8] pwm 2 duty high byte this byte with pwm 2l controls the duty of the output signal p g2 from pwm generator . pwm 3 h C pwm 3 duty high byte 7 6 5 4 3 2 1 0 pwm 3 [15:8] r/w address: d 5 h reset v alue: 0000 0000b bit name description 7 :0 pwm 3 [15:8] pwm 3 duty high byte this byte with pwm 3 l controls the duty of the output signal p g 3 from pwm generator . pnp C pwm negative polarity 7 6 5 4 3 2 1 0 - - pnp5 pnp4 pnp3 pnp2 pnp1 pnp0 - - r/w r/w r/w r /w r/w r/w address: d6h reset value: 0000 0000b bit name description n pnp n pwmn negative polarity output enable 0 = pwmn signal outputs directly on pwmn pin. 1 = pwmn signal outputs inversely on pwmn pin.
N76E003 datasheet jun 26 , 201 7 page 63 of 267 rev. 1.02 fbd C pwm fault brake data 7 6 5 4 3 2 1 0 fbf fbinls fbd5 fbd4 fbd3 fbd2 fbd1 fbd0 r/w r/w r/w r/w r/w r/w r/w r/w address: d7h reset value: 0000 0000b bit name description 7 fbf fault brake flag this flag is set when fbinen is set as 1 and fb pin detects an edge, which matches fbinls (fbd.6) sele ction . this bit is cleared by software. after fbf is cleared, fault brake data output will not be released until pwmrun (pwmcon0. 7 ) is set. 6 fbinls fb pin input level selection 0 = falling edge. 1 = rising edge. n fb dn pwmn fault brake data 0 = pwmn sig nal is overwritten by 0 once fault brake asserted . 1 = pwmn signal is overwritten by 1 once fault brake asserted . pwmcon0 C pwm control 0 (bit - addressable) 7 6 5 4 3 2 1 0 pwmrun load pwmf clrpwm - - - - r/w r/w r/w r/w - - - - address: d8h reset value : 0000 0000b bit name description 7 pwmrun pwm run enable 0 = pwm stays in idle. 1 = pwm starts running. 6 load pwm new period and duty load this bit is used to load period and duty control registers in their buffer if new period or duty value needs to b e updated. the loading will act while a pwm period is completed. the new period and duty affect ed on the next pwm cycle. after the loading is complete, load will be automatically cleared via hardware. the meaning of writing and reading load bit is differen t. writing: 0 = no effect. 1 = load new period and duty in their buffers while a pwm period is completed. reading: 0 = a loading of new period and duty is finished. 1 = a loading of new period and duty is not yet finished. 5 pwmf pwm flag this flag is set according to definitions of intsel[ 2 :0] and inttyp[1:0] in pwm intc . this bit is cleared by software.
N76E003 datasheet jun 26 , 201 7 page 64 of 267 rev. 1.02 bit name description 4 clrpwm clear pwm counter setting this bit clears the value of pwm 1 6 - bit counter for resetting to 0 000h. after the counter value is cleared, clrpwm will be automatically cleared via hardware. the meaning of writing and reading clrpwm bit is different. writing: 0 = no effect. 1 = clearing pwm 1 6 - bit counter. reading: 0 = pwm 1 6 - bit counter is completely cleared. 1 = pwm 1 6 - bit counter is not yet cl eared. pwmpl C pwm period low byte 7 6 5 4 3 2 1 0 pwmp[7:0] r/w address: d9h reset value: 0000 0000b bit name description 7:0 pwmp[7:0] pwm period low byte this byte with pwmph controls the period of the pwm generator signal. pwm0l C pwm0 duty low b yte 7 6 5 4 3 2 1 0 pwm0[7:0] r/w address: dah reset value: 0000 0000b bit name description 7:0 pwm0[7:0] pwm0 duty low byte this byte with pwm0h controls the duty of the output signal p g 0 from pwm generator . pwm1l C pwm/1 duty low byte 7 6 5 4 3 2 1 0 pwm1[7:0] r/w address: d b h reset value: 0000 0000b bit name description 7:0 pwm1[7:0] pwm 1 duty low byte this byte with pwm 1 h controls the duty of the output signal p g1 from pwm generator .
N76E003 datasheet jun 26 , 201 7 page 65 of 267 rev. 1.02 pwm2l C pwm2 duty low byte 7 6 5 4 3 2 1 0 pwm2[7:0] r/w address: d c h reset value: 0000 0000b bit name description 7:0 pwm2[7:0] pwm 2 duty low byte this byte with pwm 2 h controls the duty of the output signal p g2 from pwm generator . pwm 3 l C pwm 3 duty low byte 7 6 5 4 3 2 1 0 pwm 3 [7:0] r/w address: d d h reset value: 0000 0000b bit name description 7:0 pwm 3 [7:0] pwm 3 duty low byte this byte with pwm 3 h controls the duty of the output signal p g 3 from pwm generator . pio con0 C pwm or i/o select 7 6 5 4 3 2 1 0 - - pio 0 5 pio 0 4 pio 0 3 pio 0 2 pio 0 1 pio 0 0 - - r/w r/w r/w r/w r/w r/w address: deh reset value: 0000 0000b bit name description 5 pio 0 5 p0. 3 /pwm5 pin function select 0 = p0. 3 /pwm5 pin functions as p0. 3 . 1 = p0. 3 /pwm5 pin functions as pwm5 output. 4 pio 0 4 p 0 .1 /pwm4 pin function select 0 = p 0 .1 /pwm4 pin func tions as p 0 .1 . 1 = p 0 .1 /pwm4 pin functions as pwm4 output. 3 pio 0 3 p0. 0 /pwm3 pin function select 0 = p0. 0 /pwm3 pin functions as p0. 0 . 1 = p0. 0 /pwm3 pin functions as pwm3 output. 2 pio 0 2 p 1.0 /pwm2 pin function select 0 = p 1 . 0 /pwm2 pin functions as p 1 . 0 . 1 = p 1 . 0 /pwm2 pin functions as pwm2 output. 1 pio 0 1 p1.1/pwm1 pin function select 0 = p1.1/pwm1 pin functions as p1.1. 1 = p1.1/pwm1 pin functions as pwm1 output. 0 pio 0 0 p1. 2 /pwm0 pin function select 0 = p1. 2 /pwm0 pin functions as p1. 2 . 1 = p1. 2 /pwm0 pin functions as pwm0 output.
N76E003 datasheet jun 26 , 201 7 page 66 of 267 rev. 1.02 pwmcon1 C pwm control 1 7 6 5 4 3 2 1 0 pwmmod[1:0] gp pwmtyp fbinen pwmdiv[2:0] r/w r/w r/w r/w r/w address: dfh reset value: 0000 0000b bit name description 5 gp group mode enable this bit enables the group mode. if enable d, the duty of first three pairs of pwm are decided by pwm01h and pwm01l rather than their original duty control registers. 0 = group mode disabled. 1 = group mode enabled. 2:0 pwmdiv[2:0] pwm clock divider this field decides the pre - scale of pwm clock so urce. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. a or acc C accumulator ( bit - addressable ) 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 r/w r/w r/w r/w r/w r/w r/w r/w address: e0h rese t value : 0000 0000b bit name description 7:0 acc[7:0] accumulator the a or acc register is the standard 80c51 accumulator for arithmetic operation . adccon1 C adc control 1 7 6 5 4 3 2 1 0 - stadcpx - - etgtyp[1:0] adcex adcen - r/w - - r/w r/w r/w ad dress: e1h reset value: 0000 0000b bit name description 6 stadcpx external start adc trigger pin select 0 = assign stadc to p0.4. 1 = assign stadc to p1.3. note that stadc will exchange immediately once setting or clearing this bit.
N76E003 datasheet jun 26 , 201 7 page 67 of 267 rev. 1.02 bit name description 3:2 etgtyp[1:0] exter nal trigger type select when adcex (adccon1.1) is set, these bits select which condition triggers adc conversion. 00 = falling edge on pwm0/2/4 or stadc pin. 01 = rising edge on pwm0/2/4 or stadc pin. 10 = central point of a pwm period. 11 = end point of a pwm period. note that the central point interrupt or the period point interrupt is only available for pwm center - aligned type. 1 adcex adc external conversion trigger select this bit select the methods of triggering an a/d conversion. 0 = a/d conversion is started only via setting adcs bit. 1 = a/d conversion is started via setting adcs bit or by external trigger source depending on etgsel[1:0] and etgtyp[1:0]. note that while adcs is 1 (busy in converting), the adc will ignore the following external trig ger until adcs is hardware cleared. 0 adcen adc enable 0 = adc circuit off. 1 = adc circuit on. adccon2 C adc control 2 7 6 5 4 3 2 1 0 adfben adcmpop adcmpen adcmpo - - - adcdly.8 r/w r/w r/w r - - - r/w address: e2h reset value: 0000 0000b bit name description 7 adfben adc compare result asserting fault brake enable 0 = adc asserting fault brake disabled. 1 = adc asserting fault brake enabled. fault brake is asserted once its compare result adcmpo is 1. meanwhile, pwm channels output fault brake dat a. pwmrun (pwmcon0.7) will also be automatically cleared by hardware. the pwm output resumes when pwmrun is set again. 6 adcmpop adc comparator output polarity 0 = adcmpo is 1 if adcr[ 11 :0] is greater than or equal to adcmp[ 11 :0]. 1 = adcmpo is 1 i f adcr[ 11 :0] is less than adcmp[ 11 :0]. 5 adcmpen adc result comparator enable 0 = adc result comparator disabled. 1 = adc result comparator enabled. 4 adcmpo adc comparator output value this bit is the output value of adc result comparator based on the setting of acmpop. this bit updates after every a/d conversion complete. 0 adcdly.8 adc external trigger delay counter bit 8 see adcdly register.
N76E003 datasheet jun 26 , 201 7 page 68 of 267 rev. 1.02 adcdly C adc trigger delay counter 7 6 5 4 3 2 1 0 adcdly[7:0] r/w address: e3h reset value: 0000 0000b bit name description 7:0 adcdly[7:0] adc external trigger delay counter low byte this 8 - bit field combined with adccon2.0 forms a 9 - bit counter. this counter inserts a delay after detecting the external trigger. an a/d converting starts after this period of delay. external trigger delay time = . note that this field is valid only when adcex (adccon1.1) is set. user should not modify adcdly during pwm run time if selecting pwm output as the external adc trigger source. c0l C capture 0 low byte 7 6 5 4 3 2 1 0 c0l[7:0] r/w address: e4h reset value: 0000 0000b bit name description 7:0 c0l[7:0] input capture 0 result low byte the c0l register is the low byte of the 16 - bit result captured by input capture 0 . c0h C capture 0 high byte 7 6 5 4 3 2 1 0 c0h[7:0] r/w address: e5h reset value: 0000 0000b bit name description 7:0 c0h[7:0] input capture 0 result high byte the c0h register is the high byte of the 16 - bit result captured by input capture 0 . c1l C capture 1 low byte 7 6 5 4 3 2 1 0 c 1l[7:0] r/w address: e6h reset value: 0000 0000b bit name description 7:0 c1l[7:0] input capture 1 result low byte the c1l register is the low byte of the 16 - bit result captured by input capture 1 . adc f adcdly
N76E003 datasheet jun 26 , 201 7 page 69 of 267 rev. 1.02 c1h C capture 1 high byte 7 6 5 4 3 2 1 0 c1h[7:0] r /w address: e7h reset value: 0000 0000b bit name description 7:0 c1h[7:0] input capture 1 result high byte the c1h register is the high byte of the 16 - bit result captured by input capture 1 . adccon0 C adc control 0 (bit - addressable) 7 6 5 4 3 2 1 0 adc f adcs etgsel1 etgsel0 adchs3 adchs2 adchs1 adchs0 r/w r/w r/w r/w r/w r/w r/w r/w address: e8h reset value: 0000 0000b bit name description 7 adcf adc flag this flag is set when an a/d conversion is completed. the adc result can be read. while this fla g is 1, adc cannot start a new converting . this bit is cleared by software. 6 adcs a/d converting software start trigger setting this bit 1 triggers an a/d conversion. this bit remains logic 1 during a/d converting time and is automatically cleared via ha rdware right after conversion complete. the meaning of writing and reading adcs bit is different. writing: 0 = no effect. 1 = start an a/d converting. reading: 0 = adc is in idle state. 1 = adc is busy in converting. 5:4 etgsel[1:0] external trigger s ource select when adcex (adccon1.1) is set, these bits select which pin output triggers adc conversion. 00 = pwm0. 01 = pwm2. 10 = pwm4. 11 = stadc pin. 3:0 adchs[3:0] a/d converting channel select this filed selects the activating analog input source of adc. if adcen is 0, all inputs are disconnected. 0000 = ain0. 0001 = ain1. 0010 = ain2. 0011 = ain3. 0100 = ain4. 0101 = ain5. 0110 = ain6. 0111 = ain7 1 000 = internal band - gap voltage. others = reserved .
N76E003 datasheet jun 26 , 201 7 page 70 of 267 rev. 1.02 picon C pin interrupt control 7 6 5 4 3 2 1 0 pit 67 pit45 pit3 pit2 pit1 pit0 pips[1:0] r/w r/w r/w r/w r/w r/w r/w address: e9h reset value: 0000 0000b bit name description 7 pit67 pin interrupt channel 6 and 7 type select this bit selects which type that pin interrupt channel 6 and 7 is triggered. 0 = l evel triggered. 1 = e dge triggered. 6 pit45 pin interrupt channel 4 and 5 type select this bit selects which type that pin interrupt channel 4 and 5 is triggered. 0 = l evel triggered. 1 = e dge triggered. 5 pit3 pin interrupt channel 3 type select thi s bit selects which type that pin interrupt channel 3 is triggered. 0 = l evel triggered. 1 = e dge triggered. 4 pit2 pin interrupt channel 2 type select this bit selects which type that pin interrupt channel 2 is triggered. 0 = l evel triggered. 1 = e dge tr iggered. 3 pit1 pin interrupt channel 1 type select this bit selects which type that pin interrupt channel 1 is triggered. 0 = l evel triggered. 1 = e dge triggered. 2 pit0 pin interrupt channel 0 type select this bit selects which type that pin interrupt channel 0 is triggered. 0 = l evel triggered. 1 = e dge triggered. 1:0 pips[:0] pin interrupt port select this field selects which port is active as the 8 - channel of pin interrupt. 00 = port 0. 01 = port 1. 10 = port 2. 11 = port 3. pinen C pin interrupt n egative polarity enable. 7 6 5 4 3 2 1 0 pinen7 pinen6 pinen5 pinen4 pinen3 pinen2 pinen1 pinen0 r/w r/w r/w r/w r/w r/w r/w r/w address: eah reset value: 0000 0000b bit name description n pinenn pin interrupt channel n negative polarity enable this bi t enables low - level/falling edge triggering pin interrupt channel n. the level or edge triggered selection depends on each control bit pitn in picon. 0 = low - level/falling edge detect disabled. 1 = low - level/falling edge detect enabled.
N76E003 datasheet jun 26 , 201 7 page 71 of 267 rev. 1.02 pipen C pin interr upt positive polarity enable. 7 6 5 4 3 2 1 0 pipen7 pipen6 pipen5 pipen4 pipen3 pipen2 pipen1 pipen0 r/w r/w r/w r/w r/w r/w r/w r/w address: ebh reset value: 0000 0000b bit name description n pipenn pin interrupt channel n positive polarity enable th is bit enables high - level/rising edge triggering pin interrupt channel n. the level or edge triggered selection depends on each control bit pitn in picon. 0 = high - level/rising edge detect disabled. 1 = high - level/rising edge detect enabled. pif C pin int errupt flags 7 6 5 4 3 2 1 0 pif7 pif6 pif5 pif4 pif3 pif2 pif1 pif0 r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) address: ech res et value: 0000 0000b bit name description n pifn pin interrupt channel n flag if the edge trigger is selected, this flag will be set by hardware if the channel n of pin interrupt detects an enabled edge trigger. this flag should be cleared by software. if the level trigger is selected, this flag follows the inverse of the input signals logic level on the channel n of pin interrupt. software cannot control it. c2l C capture 2 low byte 7 6 5 4 3 2 1 0 c2l[7:0] r/w address: edh reset value: 0000 0000b bi t name description 7:0 c2l[7:0] input capture 2 result low byte the c2l register is the low byte of the 16 - bit result captured by input capture 2. c2h C capture 2 high byte 7 6 5 4 3 2 1 0 c2h[7:0] r/w address: eeh reset value: 0000 0000b bit name des cription 7:0 c2h[7:0] input capture 2 result high byte the c2h register is the high byte of the 16 - bit result captured by input capture 2 .
N76E003 datasheet jun 26 , 201 7 page 72 of 267 rev. 1.02 eip C extensive interrupt priority [3] 7 6 5 4 3 2 1 0 pt2 pspi pfb pwdt ppwm pcap ppi pi2c r/w r/w r/w r/w r/w r/ w r/w r/w address: efh reset value: 0000 0000b bit name description 7 pt2 timer 2 interrupt priority low bit 6 pspi spi interrupt priority low bit 5 pfb fault brake interrupt priority low bit 4 pwdt wdt interrupt priority low bit 3 ppwm pwm interrupt priority low bit 2 pcap input capture interrupt priority low bit 1 ppi pin interrupt priority low bit 0 pi2c i 2 c interrupt priority low bit [3] eip is used in combination with the eiph to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. b C b register (bit - addressable) 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 r/w r/w r/w r/w r/w r/w r/w r/w address: f0h rese t value: 0000 0000b bit name description 7:0 b[7:0] b register the b register is the other accumulator of the standard 80c51 .it is used mainly for mul and div instructions. capcon 3 C input capture control 3 7 6 5 4 3 2 1 0 cap13 cap12 cap11 cap10 cap03 cap02 cap01 cap00 r/w r/w r/w r/w r/w r/w r/w r/w address: f1 h reset value: 0000 0000b bit name description [7:4] cap1[3:0] input capture channel 0 input pin select 0 00 0 = p1.2/ic0 0 0 0 1 = p1.1/ic1 00 10 = p1.0/ic2 00 11 = p0.0/ic3 0100 = p0.4/ic3 0101 = p0.1/ic4 0110 = p0.3/ic5 0111 = p0.5/ic6 1000 = p1.5/ic7 others = p1.2/ic0
N76E003 datasheet jun 26 , 201 7 page 73 of 267 rev. 1.02 bit name description [3:0] cap0[3:0] input capture channel 0 input pin select 0 00 0 = p1.2/ic0 0 0 0 1 = p1.1/ic1 00 10 = p1.0/ic2 00 11 = p0.0/ic3 0100 = p0.4/ic3 0101 = p0.1/ic4 0110 = p0.3/ic5 0111 = p0.5 /ic6 1000 = p1.5/ic7 others = p1.2/ic0 capcon 4 C input capture control 4 7 6 5 4 3 2 1 0 - - - - cap23 cap22 cap21 cap20 - - - - r/w r/w r/w r/w address: f2 h reset value: 0000 0000b bit name description [3:0] cap2[3:0] input capture channel 0 input pi n select 0 00 0 = p1.2/ic0 0 0 0 1 = p1.1/ic1 00 10 = p1.0/ic2 00 11 = p0.0/ic3 0100 = p0.4/ic3 0101 = p0.1/ic4 0110 = p0.3/ic5 0111 = p0.5/ic6 1000 = p1.5/ic7 others = p1.2/ic0 spcr C serial peripheral control register 7 6 5 4 3 2 1 0 ssoe spien lsbfe mstr cpo l cpha spr1 spr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f3h , page 0 reset value: 0000 0000b bit name description 7 ssoe slave select output enable this bit is used in combination with the dismodf (spsr.3) bit to determine the feature of ? ? ? ? pin as sh own in table 14 - 1 . slave select pin configurations . this bit takes effect only under mstr = 1 and dismodf = 1 condition. 0 = ? ? ? ? functions as a general purpose i/o pin. 1 = ? ? ? ? automatically goes low for each tra nsmission when selecting external slave device and goes high during each idle state to de - select the slave device. 6 spien spi enable 0 = spi function disable d . 1 = spi function enable d .
N76E003 datasheet jun 26 , 201 7 page 74 of 267 rev. 1.02 bit name description 5 lsbfe lsb first enable 0 = the spi data is transferred msb first. 1 = the spi data is transferred lsb first. 4 mstr master mode enable this bit switches the spi operating between master and slave modes. 0 = the spi is configured as slave mode. 1 = the spi is configured as master mode. 3 cpol spi clock polarity select cpol bit determines the idle state level of the spi clock. see figure 14 - 4 . spi clock formats . 0 = the spi clock is low in idle state. 1 = the spi clock is high in idle state. 2 cpha spi clock phase select cpha bi t determines the data sampling edge of the spi clock. see figure 14 - 4 . spi clock formats . 0 = the data is sampled on the first edge of the spi clock. 1 = the data is sampled on the second edge of the spi clock. sp cr2 C serial peripheral control register 2 7 6 5 4 3 2 1 0 - - - - - - spis1 sp is0 - - - - - - r/w r/w address: f3h , page 1 reset value: 0000 0000b bit name description 7:2 - reserved
N76E003 datasheet jun 26 , 201 7 page 75 of 267 rev. 1.02 bit name description 1:0 sp is [1:0] spi interval time select ion between adjacent bytes s pis[1:0] and cpha select eight grades of spi interval time selection between adjacent bytes . as below table: cpha spis 1 spis 0 spi clock 0 0 0 0.5 0 0 1 1.0 0 1 0 1.5 0 1 1 2.0 1 0 0 1.0 1 0 1 1.5 1 1 0 2.0 1 1 1 2.5 spis [1:0] are valid only unde r master mode (ms tr = 1). spsr C serial peripheral status register 7 6 5 4 3 2 1 0 spif wcol spiovf modf dismodf - - - r/w r/w r/w r/w r/w - - - address: f4h reset value: 0000 0000b bit name description 7 spif spi complete flag this bit is set to logi c 1 via hardware while an spi data transfer is complete or an receiving data has been moved into the spi read buffer. if espi (eie .0) and ea are enabled, an spi interrupt will be required. this bit should be cleared via software. attempting to write to sp dr is inhibited if spif is set. 6 wcol write collision error flag this bit indicates a write collision event. once a write collision event occurs, this bit will be set. it should be cleared via software. 5 spiovf spi overrun error flag this bit indicates an overrun event. once an overrun event occurs, this bit will be set. if espi and ea are enabled, an spi interrupt will be required. this bit should be cleared via software. 4 modf mode fault error flag this bit indicates a mode fault error event. if ? ? ? ? pin is configured as mode fault input (mstr = 1 and dismodf = 0) and ? ? ? ? is pulled low by external devices, a mode fault error occurs. instantly modf will be set as logic 1. if espi and ea are enabled, an spi interrupt will be required. this bit should be cleared via software. 3 dismodf disable mode fault error detection this bit is used in combination with the ssoe (spcr.7) bit to determine the feature of ? ? ? ? pin as shown in table 14 - 1 . slave select pin configurations . dismodf is valid only in master mode (mstr = 1). 0 = mode fault detection en abled. ? ? ? ? serves as input pin for mode fault detection disregard of ssoe. 1 = mode fault detection d isabled. the feature of ? ? ? ? follows ssoe bit.
N76E003 datasheet jun 26 , 201 7 page 76 of 267 rev. 1.02 spdr C serial periph eral data register 7 6 5 4 3 2 1 0 spdr[7:0] r/w address: f5h reset value: 0000 0000b bit name description 7:0 spdr[7:0] serial peripheral data this byte is used for transmitting or receiving data on spi bus. a write of this byte is a write to the shif t register. a read of this byte is actually a read of the read data buffer. in master mode, a write to this register initiates transmission and reception of a byte simultaneously. aindids C adc channel digital input disconnect 7 6 5 4 3 2 1 0 p11dids p03 dids p04dids p05dids p06dids p07dids p30dids p17dids r/w r/w r/w r/w r/w r/w r/w r/w address: f6h reset value: 0000 0000b bit name description n p nn dids adc channel digital input disable 0 = adc channel n digital input enabled. 1 = adc channel n digital input disabled. adc channel n is read always 0. eiph C extensive interrupt priority high [4] 7 6 5 4 3 2 1 0 pt2h pspih pfbh pwdth ppwmh pcaph ppih pi2ch r/w r/w r/w r/w r/w r/w r/w r/w address: f7h reset value: 0000 0000b bit name description 7 pt2h timer 2 interrupt priority high bit 6 pspih spi interrupt priority high bit 5 pfbh fault brake interrupt priority high bit 4 pwdth wdt interrupt priority high bit 3 ppwmh pwm interrupt priority high bit 2 pcaph input capture interrupt priority high bi t 1 ppih pin interrupt priority high bit 0 pi2ch i 2 c interrupt priority high bit [4] eiph is used in combination with the eip to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration.
N76E003 datasheet jun 26 , 201 7 page 77 of 267 rev. 1.02 scon _ 1 C serial port 1 control (bit - addressable) 7 6 5 4 3 2 1 0 sm0 _ 1/fe _ 1 sm1 _ 1 sm2 _ 1 ren _ 1 tb8 _ 1 rb8 _ 1 ti _ 1 ri _ 1 r/w r/w r/w r/w r/w r/w r/w r/w address: f8h reset value: 0000 0000b bit na me description 7 sm0 _ 1/fe _ 1 serial port 1 mode select smod0 _ 1 (t3con.6) = 0: see table 13 - 2 . serial port 1 mode description for details. smod0 _ 1 (t3con.6) = 1: sm0 _ 1/fe _ 1 bit is used as frame error (fe) status fla g. it is cleared by software. 0 = frame error (fe) did not occur. 1 = frame error (fe) occur red and detected. 6 sm1 _ 1 5 sm2 _ 1 multiprocessor communication mode enable the function of this bit is dependent on the serial port 1 mode. mode 0: no effect. mode 1: this bit checks valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is valid only when the received stop bit is logic 1 and the received data matches given or broadcast address. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9 th bit. 1 = reception is valid only when the received 9 th bit is logic 1 and the received data matches given or broadcast address. 4 ren _ 1 receiving ena ble 0 = serial port 1 reception disabled. 1 = serial port 1 reception e nabled in mode 1,2, or 3. in mode 0, reception is initiated by the condition ren_1 = 1 and ri_1 = 0. 3 tb8 _ 1 9 th transmitted bit this bit defines the state of the 9 th transmission bit in serial port 1 mode 2 or 3. it is not used in mode 0 or 1. 2 rb8 _ 1 9 th received bit the bit identifies the logic level of the 9 th received bit in serial port 1 mode 2 or 3. in mode 1, rb8 _ 1 is the logic level of the received stop bit. sm2 _ 1 bit as logic 1 has restriction for exception. rb8 _ 1 is not used in mode 0. 1 ti _ 1 transmission interrupt flag this flag is set by hardware when a data frame has been transmitted by the serial port 1 after the 8 th bit in mode 0 or the last data bit in other modes. wh en the serial port 1 interrupt is enabled, setting this bit causes the cpu to execute the serial port 1 interrupt service routine. this bit must be cleared manually via software.
N76E003 datasheet jun 26 , 201 7 page 78 of 267 rev. 1.02 bit na me description 0 ri _ 1 receiving interrupt flag this flag is set via hardware when a data fr ame has been received by the serial port 1 after the 8 th bit in mode 0 or after sampling the stop bit in mode 1, 2, or 3. sm2 _ 1 bit as logic 1 has restriction for exception. when the serial port 1 interrupt is enabled, setting this bit causes the cpu to ex ecute to the serial port 1 interrupt service routine. this bit must be cleared manually via software. pdten C pwm dead - time enable ( ta protected ) 7 6 5 4 3 2 1 0 - - - pdtcnt.8 - pdt45en pdt23en pdt01en - - - r/w - r/w r/w r/w address: f9h reset value: 0000 0000b bit name description 4 pdtcnt.8 pwm dead - time counter bit 8 see pdtcnt register. 2 pdt45en pwm4/5 pair dead - time insertion enable this bit is valid only when pwm4/5 is under complementary mode. 0 = no delay on gp4/gp5 pair signals. 1 = insert dead - time delay on the rising edge of gp4/gp5 pair signals. 1 pdt23en pwm2/3 pair dead - time insertion enable this bit is valid only when pwm2/3 is under complementary mode. 0 = no delay on gp2/gp3 pair signals. 1 = insert dead - time delay on the rising ed ge of gp2/gp3 pair signals. 0 pdt01en pwm0/1 pair dead - time insertion enable this bit is valid only when pwm0/1 is under complementary mode. 0 = no delay on gp0/gp1 pair signals. 1 = insert dead - time delay on the rising edge of gp0/gp1 pair signals. pdtc nt C pwm dead - time counter ( ta protected ) 7 6 5 4 3 2 1 0 pdtcnt[7:0] r/w address: fah reset value: 0000 0000b bit name description 7:0 pdtcnt[7:0] pwm dead - time counter low byte this 8 - bit field combined with pdten.4 forms a 9 - bit pwm dead - time counte r pdtcnt. this counter is valid only when pwm is under complementary mode and the correspond pdten bit for pwm pair is set. pwm dead - time = . note that user should not modify pdtcnt during pwm run time. sys f 1 pdtcnt ?
N76E003 datasheet jun 26 , 201 7 page 79 of 267 rev. 1.02 pmen C pwm mask enable 7 6 5 4 3 2 1 0 - - pmen5 pmen4 pmen3 pmen2 pmen1 pmen0 - - r/w r/w r/w r/w r/w r/w address: fbh reset value: 0000 0000b bit name description n pmenn pwmn mask enable 0 = pwmn signal outputs from its pwm generator. 1 = pwmn signal is masked by pmdn. pmd C pw m mask data 7 6 5 4 3 2 1 0 - - pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 - - r/w r/w r/w r/w r/w r/w address: fch reset value: 0000 0000b bit name description n pmdn pwmn mask data the pwmn signal outputs mask data once its corresponding pmenn is set. 0 = pwmn si gnal is masked by 0 . 1 = pwmn signal is masked by 1 . pordis C por disable ( ta protected ) 7 6 5 4 3 2 1 0 pordis[7:0] w address: fdh, page: 0 reset value: 0000 0000b bit name description 7:0 por dis[7:0] por disable to first writing 5ah to the pordis an d immediately followed by a writing of a5h will disable por. notice: strongly suggests that disabl e por function after power - on reset at the initial part of customer code. p lease reference 24.1 power - o n reset (por) for more detail information. eip1 C extensive interrupt priority 1 [ 5 ] 7 6 5 4 3 2 1 0 - - - - - pwkt pt3 ps _ 1 - - - - - r/w r/w r/w address: feh, page: 0 reset value: 0000 0000b bit name description 2 pwkt wkt interrupt priority low bit 1 pt3 timer 3 interrupt priority low bit 0 ps _ 1 serial port 1 interrupt priority low bit
N76E003 datasheet jun 26 , 201 7 page 80 of 267 rev. 1.02 [5] eip1 is used in combination with the eiph1 to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. eiph1 C extensive interrupt priority high 1 [ 6 ] 7 6 5 4 3 2 1 0 - - - - - pwkth pt3h psh _ 1 - - - - - r/w r/w r/w address: ffh, page: 0 reset value: 00 00 0000b bit name description 2 pwkth wkt interrupt priority high bit 1 pt3h timer 3 interrupt priority high bit 0 psh _ 1 serial port 1 interrupt priority high bit [6] eiph1 is used in combination with the eip1 to determine the priority of each interrup t source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration.
N76E003 datasheet jun 26 , 201 7 page 81 of 267 rev. 1.02 7. i/o port structure a nd operation the N76E003 has a maximum of 26 bit - addressable general i/o pin s grouped a s 4 ports, p0 to p3. each port has its port control register (px register). the writing and reading of a port control register have different meanings. a write to port control register sets the port output latch logic value, whereas a read gets the port pi n logic state. all i/o pin s except p2.0 can be configured individually as one of four i/o modes by software. these four modes are quasi - bidirectional (standard 8051 port structure), push - pull, input - only , and open - drain modes. each port spends two special function registers pxm1 and pxm2 to select the i/o mode of port px. the list below illustrates how to select the i/o mode of px. n . note that the default configuration of is input - only (high - impedance) after any reset . table 7 - 1 . configuration for different i/o modes pxm1. n pxm2. n i/o type 0 0 quasi - bidirectional 0 1 push - pull 1 0 input - only (high - impedance) 1 1 open - drain all i/o pins can be selected as ttl level inputs or schmitt triggered inputs by sele cting corresponding bit in p xs register. s chmitt triggered input has better glitch suppression capability. all i/o pins also have bit - controllable, slew rate select ability via software. the control registers are pxsr. by default, the slew rate is slow . if user would like to increase the i/o output speed, setting the corresponding bit in pxsr, the slew rate is selected in a faster level. p2.0 is configured as an input - only pin when programming rpd (config0.2) as 0. meanwhile, p2.0 is permanent in input - only mode and schmitt triggered type. p2.0 also has an internal pull - up enabled by p 20 up (p 2s . 7 ) . if rpd remains un - programmed, p2.0 pin functions as an external reset pin and p2.0 is not available. a read of p2.0 bit is always 0. meanwhile, the internal pull - up is always enabled. 7.1 quasi - bidirectional mode the quasi - bidirectional mode, as the standard 8051 i/o structure, can rule as both input and output. when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. wh en the pin is pulled low, it is driven strongly and able to sink a large current. in the quasi - bidirectional i/o structure, there are three pull - high transistors. each of them serves different purposes. one of these pull - highs, called the very weak pull - high, is turned on whenever the port latch contains logic 1 . he very weak pull - high sources a very small current that will pull the pin high if it is left floating.
N76E003 datasheet jun 26 , 201 7 page 82 of 267 rev. 1.02 a second pull - high, called the weak pull - high, is turned on when the outside port pin itself is at logic 1 level. this pull - high provides the primary source current for a quasi - bidirectional pin that is outputting 1 . if a pin which has logic 1 on it is pulled low by an external device, the weak pull - high turns off, and only the very weak pull - high remains on. to pull the pin low under these conditions, the external device has to sink enough current (larger than i tl ) to overcome the weak pull - high and make the voltage on the port pin below its input threshold (lower than v il ). the third pull - high is the strong pull - high. this pull - high is used to speed up 0 - to - 1 transitions on a quasi - bidirectional port pin when the port latch changes from logic 0 to logic 1 . when this occurs, the strong pull - high turns on for two - cpu - clock time to pul l the port pin high quickly. then it turns off and weak and very weak pull - highs continue remaining the port pin high. the quasi - bidirectional port structure is shown below. figure 7 - 1 . quasi - bidirectional mode structure 7.2 push - p ull mode the push - pull mode has the same pull - low structure as the quasi - bidirectional mode, but provides a continuous strong pull - high when the port latch is written by logic 1 . the push - pull mode is ge nerally used as output pin when more source current is needed for an output driving. p o r t p i n 2 - c p u - c l o c k d e l a y i n p u t p o r t l a t c h p p p n v d d s t r o n g v e r y w e a k w e a k
N76E003 datasheet jun 26 , 201 7 page 83 of 267 rev. 1.02 figure 7 - 2 . push - p ull mode structure 7.3 input - only mode input - only mode provides true high - imped ance input path. although a quasi - bidirectional mode i/o can also be an input pin, but it requires relative strong input source. input - only mode also benefits to power consumption reduction for logic 0 input always consumes current from v dd if in quasi - bid irectional mode. user needs to take care that an input - only mode pin should be given with a determined voltage level by external devices or resistors. a floating pin will induce leakage current especially in power - down mode. fi gure 7 - 3 . input - only mode structure 7.4 open - d rain mode the open - drain mode turns off all pull - high transistors and only drives the pull - low of the port pin when the port latch is given by logic 0 . if the port la tch is logic 1 , it behaves as if in input - only mode. to be used as an output pin generally as i 2 c lines, a n open - drain pin should add an external pull - high, typically a resistor tied to v dd . user needs to take care that an open - drain pin with its port latc h as logic 1 should be given with a determined voltage level by external devices or resistors. a floating pin will induce leakage current especially in power - down mode. p o r t p i n i n p u t p o r t l a t c h p n v d d s t r o n g p o r t p i n i n p u t
N76E003 datasheet jun 26 , 201 7 page 8 4 of 267 rev. 1.02 figure 7 - 4 . open - d rain mode structure 7.5 read - modify - w rite instructions nstructions that read a byte from f or internal a , modify it, and rewrite it back, are called ead - modify - write instructions. when the destination is an o port or a port bit, these instru ctions read the internal output latch rather than the external pin state. this kind of instructions read the port sfr value, modify it and write back to the port sfr. all read - modify - w rite instructions are listed as follows. instruction description anl logical and. (anl direct , a and anl direct , #data ) orl logical or. (orl direct , a and orl direct , #data ) xrl logical exclusive or. ( xrl direct, a and xrl direct, #data ) jbc jump if bit = 1 and clear it. (jbc bit , rel ) cpl complement bit. (cpl bit ) inc increment. (inc direct ) dec decrement. (dec direct ) djnz decrement and jump if not zero. (djnz direct , rel ) mov bit , c move carry to bit . (mov bit, c) clr bit clear bit. (clr bit) setb bit set bit. (setb bit) the last three seem not obviously ead - mod ify - w rite instructions but actually they are. they read the entire port latch value, modify the changed bit, and then write the new value back to the port latch. 7.6 control registers of i/o ports the N76E003 has a lot of i/o control registers to provide flex ibility in all kind s of applications. the sfrs related with i/o ports can be categorized into four groups: input and output control, output mode control, input type and sink current control, and output slew rate control. all of sfrs are listed as follows. p o r t p i n i n p u t p o r t l a t c h n
N76E003 datasheet jun 26 , 201 7 page 85 of 267 rev. 1.02 input and output data control 7.6.1 these registers are i/o input and output data buffers. reading gets the i/o input data. writing forces the data output. all of these registers are bit - addressable. p0 C port 0 ( bit - addressable ) 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 r/w r/w r/w r/w r/w r/w r/w r/w address: 80h reset value : 1111 1111b bit name description 7:0 p0[7:0] port 0 port 0 is an maximum 8 - bit general purpose i/o port. p1 C port 1 ( bit - addressable ) 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1. 4 p1.3 p1.2 p1.1 p1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: 90h reset value : 1111 1111b bit name description 7:0 p1 [7:0] port 1 port 1 is an maximum 8 - bit general purpose i/o port. p2 C port 2 ( bit - addressable ) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 p2.0 r r r r r r r r address: a0h reset value : 0000 000 x b bit name description 7:1 0 reserved the bits are always read as 0. 0 p2 . 0 port 2 bit 0 p2.0 is an input - only pin when rpd (config0.2) is programmed as 0. when leaving rpd un - programmed, p2.0 is always read as 0.
N76E003 datasheet jun 26 , 201 7 page 86 of 267 rev. 1.02 p3 C port 3 ( bit - addressable ) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 p3.0 r r r r r r r r/w address: b0h reset value : 0000 000 1b bit name description 7: 1 0 reserved the bits are always read as 0. 0 p3.0 port 3 bit 0 p 3.0 is available only when the internal oscillator is used as the system clock. at this moment, p3.0 functions as a general purpose i/o. if the system clock is not selected as the internal oscillator , p3.0 pin functions as oscin . a write to p3.0 is invalid and p3.0 is always read as 0. output mode control 7.6.2 these registers control output mode which is configurable among four modes: input - only, quasi - bidirectional, push - pull, or open - drain. each pin can be configured individually. there is also a pull - up control for p2.0 in p2 s . 7 . p0m1 C p ort 0 mode select 1 [ 1 ] 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b1h , page: 0 reset value : 1111 1111b bit name description 7:0 p0m1[7:0] port 0 mode select 1 p0m2 C port 0 mode sel ect 2 [ 1 ] 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2.5 p0m2.4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b2h , page: 0 reset value : 0000 0000b bit name description 7:0 p0m2[7:0] port 0 mode select 2 [ 1 ] p0m1 and p0m2 are used in combin ation to determine the i/o mode of each pin of p0. see table 7 - 1 . configuration for different i/o modes .
N76E003 datasheet jun 26 , 201 7 page 87 of 267 rev. 1.02 p1m1 C port 1 mode select 1 [ 2 ] 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b3h, page: 0 reset value: 1111 11 11b bit name description 7 :0 p 1 m1[ 7 :0] port 1 mode select 1 p1m2 C port 1 mode select 2 [ 2 ] 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 p1m2.5 p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 r/w r/w r/w r/w r/ w r/w r/w r/w address: b4h, page: 0 reset value: 0000 0000b bit name description 7 :0 p 1 m2[ 7 :0] port 1 mode select 2. [2] p1m1 and p1m2 are used in combination to determine the i/o mode of each pin of p1. see table 7 - 1 . configuration for different i/o modes . p 1 m1.n p 1 m2.n i/o type 0 0 quasi - bidirectional 0 1 push - pull 1 0 input - only (high - impedance) 1 1 open - drain p2s C p 20 s etting and timer01 output enable 7 6 5 4 3 2 1 0 p20 up - - - t1oe t0oe - p2s.0 r/w - - - r/w r/w - r/w address: b5h reset value: 0000 0000b bit name description 7 p20 up p2.0 pull - up enable 0 = p2.0 pull - up disabled. 1 = p2.0 pull - up enabled. this bit is valid only when rpd (config0.2) is programmed as 0. when selecting as a ? ? ? ? ? ? pin, the pull - up is always enabled.
N76E003 datasheet jun 26 , 201 7 page 88 of 267 rev. 1.02 p3m1 C port 3 mode select 1 7 6 5 4 3 2 1 0 - - - - - - - p3m1.0 [ 3 ] - - - - - - - r/w address: ach, page: 0 reset value: 0000 000 1b bit name description 0 p3m1 . 0 port 3 mode select 1 p3m2 C port 3 mode select 2 7 6 5 4 3 2 1 0 - - - - - - - p3m2.0 [ 3 ] - - - - - - - r/w address: adh, page: 0 reset value: 0000 0000b bit name description 0 p3m2 . 0 port 3 mode select 2 [ 3 ] p3m1 and p3m2 are used in combination to determine the i/o mode of each pin of p3. see table 7 - 1 . configuration for different i/o modes . p 3 m1.n p 3 m2.n i/o type 0 0 quasi - bidirectional 0 1 push - pull 1 0 input - only (high - impedance) 1 1 open - drain input type 7.6.3 each i/o pin can be configured individually as ttl input or schmitt triggered input. note that all of pxs registers are accessible by switching sfr page to page 1. p0s C port 0 schmitt triggered input 7 6 5 4 3 2 1 0 p 0s .7 p 0s .6 p 0s .5 p 0s .4 p 0s .3 p 0s .2 p 0s .1 p 0s .0 r/w r/w r/w r/w r/w r/w r/w r/w addres s: b1h, page: 1 reset value: 0000 0000 b bit name description n p 0s .n p0.n schmitt triggered input 0 = ttl level input of p0.n. 1 = schmitt triggered input of p0.n.
N76E003 datasheet jun 26 , 201 7 page 89 of 267 rev. 1.02 p1s C port 1 schmitt triggered input 7 6 5 4 3 2 1 0 p1s.7 p1s.6 p1s.5 p1s.4 p1s.3 p1s.2 p1s.1 p1s.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b3h, page: 1 reset value: 0000 0000 b bit name description 7 p1s.7 p1.7 schmitt triggered input 0 = ttl level input of p1.7. 1 = schmitt triggered input of p1.7. 6 p1s.6 p1.6 schmitt triggered input 0 = ttl level input of p1.6. 1 = schmitt triggered input of p1.6. 5 p1s. 5 p1. 5 schmitt triggered input 0 = ttl level input of p1. 5 . 1 = schmitt triggered input of p1. 5 . 4 p1s. 4 p1. 4 schmitt triggered input 0 = ttl level input of p1. 4 . 1 = schmitt triggere d input of p1. 4 . 3 p1s. 3 p1. 3 schmitt triggered input 0 = ttl level input of p1. 3 . 1 = schmitt triggered input of p1. 3 . 2 p1s.2 p1.2 schmitt triggered input 0 = ttl level input of p1.2. 1 = schmitt triggered input of p1.2. 1 p1s.1 p1.1 schmitt triggered input 0 = ttl level input of p1.1. 1 = schmitt triggered input of p1.1. 0 p1s.0 p1.0 schmitt triggered input 0 = ttl level input of p1.0. 1 = schmitt triggered input of p1.0. p2s C p 20 s etting and timer01 output enable 7 6 5 4 3 2 1 0 p20 up - - - t1oe t0oe - p2s.0 r/w - - - r/w r/w - r/w address: b5h reset value: 0000 0000b bit name description 0 p2s. 0 p2. 0 schmitt triggered input 0 = ttl level input of p2. 0 . 1 = schmitt triggered input of p2. 0 .
N76E003 datasheet jun 26 , 201 7 page 90 of 267 rev. 1.02 p3s C port 3 schmitt triggered input 7 6 5 4 3 2 1 0 - - - - - - - p3s.0 - - - - - - - r/w address: ach, page: 1 reset value: 0000 0000 b bit name description 0 p3 s . 0 p3. 0 schmitt triggered input 0 = ttl level input of p3. 0 . 1 = schmitt triggered input of p3. 0 . output slew rate control 7.6.4 slew rate for e ach i/o pin is configur able individually. by default, each pin is in normal slew rate mode. user can set each control register bit to enable high - speed slew rate for the corresponding i/o pin. note that all pxsr registers are accessible by switching sfr page t o page 1. p0sr C port 0 slew rate 7 6 5 4 3 2 1 0 p0sr.7 p0sr.6 p0sr.5 p0sr.4 p0sr.3 p0sr.2 p0sr.1 p0sr.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b2h, page: 1 reset value: 0000 0000b bit name description n p0sr.n p0.n slew rate 0 = p0.n normal output slew rate . 1 = p0.n high - speed output slew rate . p1sr C port 1 slew rate 7 6 5 4 3 2 1 0 p1sr.7 p1sr.6 p1sr.5 p1sr.4 p1sr.3 p1sr.2 p1sr.1 p1sr.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b4h, page: 1 reset value: 0000 0000b bit name description n p1sr .n p1.n slew rate 0 = p1.n normal output slew rate . 1 = p1.n high - speed output slew rate .
N76E003 datasheet jun 26 , 201 7 page 91 of 267 rev. 1.02 p3sr C port 3 slew rate 7 6 5 4 3 2 1 0 - - - - - - - p3sr.0 - - - - - - - r/w address: adh, page: 1 reset value: 0000 0000b bit name description 0 p3sr. 0 p3.n s lew rate 0 = p3. 0 normal output slew rate . 1 = p3. 0 high - speed output slew rate .
N76E003 datasheet jun 26 , 201 7 page 92 of 267 rev. 1.02 8. timer/counter 0 and 1 timer/counter 0 and 1 on N76E003 are two 16 - bit timers/counters. each of them has two 8 - bit registers those form the 16 - bit counting register. for time r/counter 0 they are th0, the upper 8 - bit register, and tl0, the lower 8 - bit register. similarly timer/counter 1 has two 8 - bit registers, th1 and tl1. tcon and tmod can configure modes of timer/counter 0 and 1. the timer or counter function is selected by the ? bit in tmod. each timer/counter has its own selection bit. tmod.2 selects the function for timer/counter 0 and tmod.6 selects the function for timer/counter 1 when configured as a timer , the timer counts the system clock cycles. the timer clock is 1/12 of the system clock (f sys ) for standard 8051 capability or direct the system clock for enhancement, which is selected by t0m (ckcon.3) bit for timer 0 and t1m (ckcon.4) bit for timer 1. in the counter mode, the countering register increases on t he falling edge of the external input pin t0. if the sampled value is high in one clock cycle and low in the next, a valid 1 - to - 0 transition is recognized on t0 or t1 pin. the timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. the same device pins that are used for the t0 and t1 count inputs are also used for the timer toggle outputs. this function is enabled by control bits t0oe and t1oe in the p 2 s register, and apply to timer 0 and timer 1 respectively . the port outputs will be logic 1 prior to the first timer overflow when this mode is turned on. in order for this mode to function, the ? bit should be cleared selecting the system clock as the clock source for the timer. note that the th0 (th1) and tl0 (tl1) are accessed separately. it is strongly recommended that in mode 0 or 1, user should stop timer temporally by clearing tr0 (tr1) bit before reading from or writing to th0 (th1) and tl0 (tl1). the free - running reading or writing may cause unpredic table result. tmod C timer 0 and 1 mode 7 6 5 4 3 2 1 0 gate ? m1 m0 gate ? m1 m0 r/w r/w r/w r/w r/w r/w r/w r/w address: 89h reset value: 0000 0000b bit name description 7 gate timer 1 gate control 0 = timer 1 will clock when tr1 is 1 regardl ess of ? ? ? ? ? ? ? logic level. 1 = timer 1 will clock only when tr1 is 1 and ? ? ? ? ? ? ? is logic 1 .
N76E003 datasheet jun 26 , 201 7 page 93 of 267 rev. 1.02 bit name description 6 ? timer 1 counter/timer select 0 = timer 1 is incremented by internal system clock. 1 = timer 1 is incremented by the falling edge of the external pin t1. 5 m1 timer 1 mode select m 1 m 0 timer 1 mode 0 0 mode 0: 13 - bit timer/counter 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th1 1 1 mode 3 : timer 1 halted 4 m0 3 gate timer 0 gate control 0 = timer 0 will clo ck when tr 0 is 1 regardless of ? ? ? ? ? ? ? logic level. 1 = timer 0 will clock only when tr 0 is 1 and ? ? ? ? ? ? ? is logic 1 . 2 ? timer 0 counter/timer select 0 = timer 0 is incremented by internal system clock. 1 = timer 0 is incremented by the falling edge of the external pin t0. 1 m1 timer 0 mode select m 1 m 0 timer 0 mode 0 0 mode 0: 13 - bit timer/counter 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th0 1 1 mode 3 : tl0 as a 8 - bit timer/counter and th0 as a 8 - bit t imer 0 m0 tcon C timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r (level) r/w (edge) r/w r (level) r/w (edge) r/w address: 88h reset value: 0000 0000b bit name description 7 tf1 timer 1 over flow flag this bit is set when timer 1 overflows. it is automatically cleared by hardware when the program executes the timer 1 interrupt service routine. this bit can be set or cleared by software. 6 tr1 timer 1 run control 0 = timer 1 disabled . clearing this bit will halt timer 1 and the current count will be preserved in th1 and tl1. 1 = timer 1 e nabled. 5 tf0 timer 0 overflow flag this bit is set when timer 0 overflows. it is automatically cleared via hardware when the program executes the timer 0 int errupt service routine. this bit can be set or cleared by software. 4 tr0 timer 0 run control 0 = timer 0 disabled . clearing this bit will halt timer 0 and the current count will be preserved in th0 and tl0. 1 = timer 0 e nabled.
N76E003 datasheet jun 26 , 201 7 page 94 of 267 rev. 1.02 tl0 C timer 0 low byte 7 6 5 4 3 2 1 0 tl0[7:0] r/w address: 8ah reset value: 0000 0000b bit name description 7:0 tl0[7:0] timer 0 low byte the tl0 register is the low byte of the 16 - bit counting register of timer 0. th0 C timer 0 high byte 7 6 5 4 3 2 1 0 th0[7:0] r/w add ress: 8ch reset value: 0000 0000b bit name description 7:0 th0[7:0] timer 0 high byte the t h 0 register is the high byte of the 16 - bit counting register of timer 0. tl1 C timer 1 low byte 7 6 5 4 3 2 1 0 tl1[7:0] r/w address: 8bh reset value: 0000 0000 b bit name description 7:0 tl1[7:0] timer 1 low byte the tl 1 register is the low byte of the 16 - bit counting register of timer 1 . th1 C timer 1 high byte 7 6 5 4 3 2 1 0 th1[7:0] r/w address: 8dh reset value: 0000 0000b bit name description 7:0 th1[7 :0] timer 1 high byte the t h1 register is the high byte of the 16 - bit counting register of timer 1 .
N76E003 datasheet jun 26 , 201 7 page 95 of 267 rev. 1.02 ckcon C clock control 7 6 5 4 3 2 1 0 - pwmcks - t1m t0m - cloen - - r/w - r/w r/w - r/w - address: 8eh reset value: 0000 0000b bit name description 4 t1m timer 1 clock mode select 0 = the clock source of timer 1 is the system clock divided by 12. it maintains standard 8051 compatibility. 1 = the clock source of timer 1 is direct the system clock. 3 t0m timer 0 clock mode select 0 = the clock source of timer 0 is the system clock divided by 12. it maintains standard 8051 compatibility. 1 = the clock source of timer 0 is direct the system clock. p2s C p 20 s etting and timer01 output enable 7 6 5 4 3 2 1 0 p20 up - - - t1oe t0oe - p2s.0 r/w - - - r/w r/w - r/w address: b5h reset value: 0000 0000b bit name description 3 t1oe timer 1 output enable 0 = timer 1 output disabled. 1 = timer 1 output enabled from t1 pin. ote that imer output should be enabled only when operating in its imer mode. 2 t0oe timer 0 output enable 0 = timer 0 output disabled. 1 = timer 0 output enabled from t0 pin. ote that imer output should be enabled only when operating in its imer mode. 8.1 mode 0 (13 - bit timer) in mode 0, the timer/counter is a 13 - bit counter. the 13 - bit counter consists of th0 (th1) and the five lower bits of tl0 (tl1). the upper three bits of tl0 (tl1) are ignored. the timer/counter is enabled when tr0 (tr1) is set and either gate is 0 or ? ? ? ? ? ? ? ( ? ? ? ? ? ? ? ) is 1. gate setting as 1 allows the timer to ca lculate the pulse width on external input pin ? ? ? ? ? ? ? ( ? ? ? ? ? ? ? ). when the 13 - bit value moves from 1fffh to 0000h, the timer overflow flag tf0 (tf1) is set and an interrupt occurs if enabled.
N76E003 datasheet jun 26 , 201 7 page 96 of 267 rev. 1.02 figure 8 - 1 . timer/counters 0 and 1 in mode 0 8.2 mode 1 (16 - bit timer) mode 1 is similar to mode 0 except that the counting registers are fully used as a 16 - bit counter. roll - over occurs when a count moves ffffh to 0000h. the timer overflow flag tf0 (tf1) of the relevant timer/counter is set and an interrupt will occurs if enabled. figure 8 - 2 . timer/counters 0 and 1 in mode 1 8.3 mode 2 (8 - bit auto - reload timer) in mode 2, the timer/counter is in auto - reload mode. in this mode, tl0 (tl1) acts as an 8 - bit count register whereas th0 (th1) holds the reload value. when the tl0 (tl1) register overflow, the tf0 (tf1) bit in tcon is set and tl0 (tl1) is reloaded with the contents of th 0 (th1) and the counting process continues from here. the reload operation leaves the contents of the th0 (th1) register t f 0 ( t f 1 ) t h 0 ( t h 1 ) t l 0 ( t l 1 ) t i m e r i n t e r r u p t 0 4 7 0 7 t 0 ( t 1 ) p i n t 0 o e ( p 2 s . 2 ) ( t 1 o e ( p 2 s . 3 ) ) 0 1 t 0 ( t 1 ) p i n c / t g a t e t r 0 ( t r 1 ) f s y s i n t 0 ( i n t 1 ) p i n 1 / 1 2 0 1 t 0 m ( c k c o n . 3 ) ( t 1 m ( c k c o n . 4 ) ) t f 0 ( t f 1 ) t h 0 ( t h 1 ) t l 0 ( t l 1 ) t i m e r i n t e r r u p t 0 7 0 7 t 0 ( t 1 ) p i n t 0 o e ( p 2 s . 2 ) ( t 1 o e ( p 2 s . 3 ) ) 0 1 t 0 ( t 1 ) p i n c / t g a t e t r 0 ( t r 1 ) f s y s i n t 0 ( i n t 1 ) p i n 1 / 1 2 0 1 t 0 m ( c k c o n . 3 ) ( t 1 m ( c k c o n . 4 ) )
N76E003 datasheet jun 26 , 201 7 page 97 of 267 rev. 1.02 unchanged. this feature is best suitable for uart baud rate generator for it runs without continuous software intervention. note that o nly timer1 can be the baud rate source for uart. counting is enabled by setting the tr0 (tr1) bit as 1 and proper setting of gate and ? ? ? ? ? ? ? ( ? ? ? ? ? ? ? ) pins. the functions of gate and ? ? ? ? ? ? ? ( ? ? ? ? ? ? ? ) pins are just the same as mode 0 and 1. figure 8 - 3 . timer/counters 0 and 1 in mode 2 8.4 mode 3 (two separate 8 - bit timers) mode 3 has different operating methods for timer 0 and timer 1. for timer/counter 1, mode 3 simply freezes the count er. timer/counter 0, however, configures tl0 and th0 as two separate 8 bit count registers in this mode. tl0 uses the timer/counter 0 control bits ? , gate, tr0, ? ? ? ? ? ? ? , and tf0. the tl0 also can be used as a 1 - to - 0 transition counter on pin t0 as deter mined by ? (tmod.2). th0 is forced as a clock cycle counter and takes over the usage of tr1 and tf1 from timer/counter 1. mode 3 is used in case that an extra 8 bit timer is needed. if timer/counter 0 is configured in mode 3, timer/counter 1 can be tur ned on or off by switching it out of or into its own mode 3. it can still be used in modes 0, 1 and 2 although its flexibility is restricted. it no longer has control over its overflow flag tf1 and the enable bit tr1. however timer 1 can still be used as a timer/counter and retains the use of gate, ? ? ? ? ? ? ? pin and t1m. it can be used as a baud rate generator for the serial port or other application not requiring an interrupt. t f 0 ( t f 1 ) t h 0 ( t h 1 ) t l 0 ( t l 1 ) t i m e r i n t e r r u p t 0 7 0 7 t 0 ( t 1 ) p i n t 0 o e ( p 2 s . 2 ) ( t 1 o e ( p 2 s . 3 ) ) 0 1 t 0 ( t 1 ) p i n c / t g a t e t r 0 ( t r 1 ) f s y s i n t 0 ( i n t 1 ) p i n 1 / 1 2 0 1 t 0 m ( c k c o n . 3 ) ( t 1 m ( c k c o n . 4 ) )
N76E003 datasheet jun 26 , 201 7 page 98 of 267 rev. 1.02 figure 8 - 4 . timer/counter 0 in mode 3 t f 0 t h 0 t l 0 t i m e r 0 i n t e r r u p t 0 7 0 7 t f 1 t i m e r 1 i n t e r r u p t t r 1 g a t e t r 0 i n t 0 p i n t 0 p i n t 0 o e ( p 2 s . 2 ) t 1 p i n t 1 o e ( p 2 s . 3 ) 0 1 t 0 p i n c / t f s y s 1 / 1 2 0 1 t 0 m ( c k c o n . 3 )
N76E003 datasheet jun 26 , 201 7 page 99 of 267 rev. 1.02 9. timer 2 and input ca pture timer 2 is a 16 - bit up counter cascaded with th2, the upper 8 bits register, and tl2, the lower 8 bit register. equipped with rcmp2h and rcmp2l, timer 2 can operate under compare mode and auto - rel oad mode selected by ? ? ? ? ? ? (t2con.0). an 3 - channel input capture module makes timer 2 detect and measure the width or period of input pulses. the results of 3 input captures are stores in c0h and c0l, c1h and c1l, c2h and c2l individually. the clock sou rce of timer 2 is from the system clock pre - scaled by a clock divider with 8 different scales for wide field application. the clock is enabled when tr2 (t2con.2) is 1, and disabled when tr2 is 0. the following registers are related to timer 2 function. figure 9 - 1 . timer 2 block diagram t f 2 t i m e r 2 i n t e r r u p t p r e - s c a l a r f s y s r c m p 2 h t 2 d i v [ 2 : 0 ] ( t 2 m o d [ 6 : 4 ] ) r c m p 2 l 0 0 0 1 1 0 1 1 c a p f 0 c a p f 1 c a p f 2 l d e n [ 1 ] ( t 2 m o d . 7 ) l d t s [ 1 : 0 ] ( t 2 m o d [ 1 : 0 ] ) t r 2 ( t 2 c o n . 2 ) t i m e r 2 m o d u l e c 0 h c 0 l n o i s e f i l t e r e n f 0 ( c a p c o n 2 . 4 ) o r [ 0 0 ] [ 0 1 ] [ 1 0 ] c a p 0 l s [ 1 : 0 ] ( c a p c o n 1 [ 1 : 0 ] ) c a p e n 0 ( c a p c o n 0 . 4 ) i n p u t c a p t u r e 0 m o d u l e i n p u t c a p t u r e 1 m o d u l e i n p u t c a p t u r e 2 m o d u l e i n p u t c a p t u r e f l a g s ( c a p f [ 2 : 0 ] ) c a p c r [ 1 ] ( t 2 m o d . 3 ) c a p f 0 c a p f 1 c a p f 2 c l e a r t i m e r 2 [ 1 ] o n c e c a p c r a n d l d e n a r e b o t h s e t , a n i n p u t c a p t u r e e v e n t o n l y c l e a r s t h 2 a n d t l 2 w i t h o u t r e l o a d i n g r c m p 2 h a n d r c m p 2 l c o n t e n t s . i n p u t c a p t u r e i n t e r r u p t c a p f 0 c a p f 1 c a p f 2 c m p c r ( t 2 m o d . 2 ) c l e a r t i m e r 2 = c a p 0 c a p 1 c a p 2 t h 2 t l 2 c l e a r c o u n t e r c a p f 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 p 1 . 5 / i c 7 p 0 . 5 / i c 6 p 0 . 3 / i c 5 p 0 . 1 / i c 4 p 0 . 0 / i c 3 p 1 . 0 / i c 2 p 1 . 1 / i c 1 p 1 . 2 / i c 0 1 0 0 0 p 0 . 4 / i c 3
N76E003 datasheet jun 26 , 201 7 page 100 of 267 rev. 1.02 t2con C timer 2 control 7 6 5 4 3 2 1 0 tf2 - - - - tr2 - ? ? ? ? ? ? r/w - - - - r/w - r/w address: c8h reset value: 0000 0000b bit name descript ion 7 tf2 timer 2 overflow flag this bit is set when timer 2 overflows or a compare match occurs. if the timer 2 interrupt and the global interrupt are enable, setting this bit will make cpu execute timer 2 interrupt service routine. this bit is not autom atically cleared via hardware and should be cleared via software. 2 tr2 timer 2 run control 0 = timer 2 disabled . clearing this bit will halt timer 2 and the current count will be preserved in th2 and tl2. 1 = timer 2 e nabled. 0 ? ? ? ? ? ? timer 2 compare or auto - reload mode select this bit selects timer 2 functioning mode. 0 = auto - reload mode. 1 = compare mode. t2mod C timer 2 mode 7 6 5 4 3 2 1 0 lden t2div[2:0] capcr cmpcr ldts[1:0] r/w r/w r/w r/w r/w address: c9h reset value: 0000 0000b bit name d escription 7 lden enable auto - reload 0 = reloading rcmp2h and rcmp2l to th2 and tl2 disable d . 1 = r eloading rcmp2h and rcmp2l to th2 and tl2 en able d. 6:4 t2div[2:0] timer 2 clock divider 0 00 = timer 2 clock divider is 1/1. 0 01 = timer 2 clock divider is 1/4. 0 10 = timer 2 clock divider is 1/16. 0 11 = timer 2 clock divider is 1/32. 100 = timer 2 clock divider is 1/64. 101 = timer 2 clock divider is 1/128. 110 = timer 2 clock divider is 1/256. 111 = timer 2 clock divider is 1/512. 3 capcr capture auto - clea r this bit is valid only under timer 2 auto - reload mode. it enables hardware auto - clearing th2 and tl2 counter registers after they have been transferred in to rcmp2h and rcmp2l while a capture event occurs. 0 = timer 2 continues counting when a capture ev ent occurs. 1 = timer 2 value is auto - cleared as 0000h when a capture event occurs. 2 cmpcr compare match auto - clear this bit is valid only under timer 2 compare mode. it enables hardware auto - clearing th2 and tl2 counter registers after a compare match o ccurs. 0 = timer 2 continues counting when a compare match occurs. 1 = timer 2 value is auto - cleared as 0000h when a compare match occurs.
N76E003 datasheet jun 26 , 201 7 page 101 of 267 rev. 1.02 bit name d escription 1:0 ldts[1:0] auto - reload trigger select these bits select the reload trigger event. 00 = reload when timer 2 overfl ows. 01 = reload when input capture 0 event occurs. 10 = reload when input capture 1 event occurs. 11 = reload when input capture 2 event occurs. rcmp2l C timer 2 reload/compare low byte 7 6 5 4 3 2 1 0 rcmp2l[7:0] r/w address: cah reset value: 0000 00 00b bit name description 7:0 rcmp2l[7:0] timer 2 reload/compare low byte th is register stores the low byte of compare value when timer 2 is configured in compare mode. also it holds the low byte of the reload value in auto - reload mode. rcmp2h C timer 2 r eload/compare high byte 7 6 5 4 3 2 1 0 rcmp2h[7:0] r/w address: cbh reset value: 0000 0000b bit name description 7:0 rcmp2h[7:0] timer 2 reload/compare high byte th is register stores the high byte of compare value when timer 2 is configured in compare mode. also it holds the high byte of the reload value in auto - reload mode. tl2 C timer 2 low byte 7 6 5 4 3 2 1 0 tl2[7:0] r/w address: cch , page:0 reset value: 0000 0000b bit name description 7:0 tl2[7:0] timer 2 low byte the tl2 register is the low byte of the 16 - bit counting register of timer 2.
N76E003 datasheet jun 26 , 201 7 page 102 of 267 rev. 1.02 th2 C timer 2 high byte 7 6 5 4 3 2 1 0 th2[7:0] r/w address: cdh , page:0 reset value: 0000 0000b bit name description 7:0 th2[7:0] timer 2 high byte the th2 register is the high byte of the 16 - bit cou nting register of timer 2. note that the th2 and tl2 are accessed separately. it is strongly recommended that user stops timer 2 temporally by clearing tr2 bit before reading from or writing to th2 and tl2. the free - running reading or writing may cause un predictable result.
N76E003 datasheet jun 26 , 201 7 page 103 of 267 rev. 1.02 9.1 auto - reload mode the timer 2 is configured as auto - reload mode by clearing ? ? ? ? ? ? . in this mode rcmp2h and rcmp2l registers store the reload value. the contents in rcmp2h and rcmp2l transfer into th2 and tl2 once the auto - reload eve nt occurs if setting lden bit. the event can be the timer 2 overflow or one of the triggering event on any of enabled input capture channel depending on the ldts[1:0] (t2mod[1:0]) selection. note that once capcr (t2mod.3) is set, an input capture event onl y clears th2 and tl2 without reloading rcmp2h and rcmp2l contents. figure 9 - 2 . timer 2 auto - reload mode and input capture module functional block diagram t f 2 t i m e r 2 i n t e r r u p t p r e - s c a l a r f s y s r c m p 2 h t 2 d i v [ 2 : 0 ] ( t 2 m o d [ 6 : 4 ] ) r c m p 2 l t h 2 t l 2 0 0 0 1 1 0 1 1 c a p f 0 c a p f 1 c a p f 2 l d e n [ 1 ] ( t 2 m o d . 7 ) l d t s [ 1 : 0 ] ( t 2 m o d [ 1 : 0 ] ) t r 2 ( t 2 c o n . 2 ) t i m e r 2 m o d u l e c 0 h c 0 l n o i s e f i l t e r e n f 0 ( c a p c o n 2 . 4 ) o r [ 0 0 ] [ 0 1 ] [ 1 0 ] c a p 0 l s [ 1 : 0 ] ( c a p c o n 1 [ 1 : 0 ] ) c a p e n 0 ( c a p c o n 0 . 4 ) c a p f 0 i n p u t c a p t u r e 0 m o d u l e i n p u t c a p t u r e 1 m o d u l e i n p u t c a p t u r e 2 m o d u l e i n p u t c a p t u r e f l a g s c a p f [ 2 : 0 ] c a p c r [ 1 ] ( t 2 m o d . 3 ) c a p f 0 c a p f 1 c a p f 2 c l e a r t i m e r 2 [ 1 ] o n c e c a p c r a n d l d e n a r e b o t h s e t , a n i n p u t c a p t u r e e v e n t o n l y c l e a r s t h 2 a n d t l 2 w i t h o u t r e l o a d i n g r c m p 2 h a n d r c m p 2 l c o n t e n t s . i n p u t c a p t u r e i n t e r r u p t c a p f 0 c a p f 1 c a p f 2 c a p 0 c a p 1 c a p 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 p 1 . 5 / i c 7 p 0 . 5 / i c 6 p 0 . 3 / i c 5 p 0 . 1 / i c 4 p 0 . 0 / i c 3 p 1 . 0 / i c 2 p 1 . 1 / i c 1 p 1 . 2 / i c 0 1 0 0 0 p 0 . 4 / i c 3
N76E003 datasheet jun 26 , 201 7 page 104 of 267 rev. 1.02 9.2 compare mode timer 2 c an also be configured as the compare mode by setting ? ? ? ? ? ? . in this mode rcmp2h and rcmp2l registers serve as the compare value registers. as timer 2 up counting, th2 and tl2 match rcmp2h and rcmp2l, tf2 (t2con.7) will be set by hardware to indicate a c ompare match event. setting cmpcr (t2mod.2) makes the hardware to clear timer 2 counter as 0000h automatically after a compare match has occurred. figure 9 - 3 . timer 2 compare mod e and input capture module functional block diagram 9.3 input capture module the input capture module along with timer 2 implements the input capture function. the input capture module is configured through capcon0~2 registers. the input capture module support s 3 - channel inputs (cap0, cap1, and cap2) that share 9 i/o pins (p1.5, p1[2:0], p0.0, p0.1 and p0[5:3]). the pin mux select through capcon3 and capcon4. eac h input channel consists its own noise filter, which is enabled via setting enf0~2 (capcon2[6:4]). i t filters input glitches smaller than four system clock cycles. input capture channels has their own independent edge detector but share the unique timer 2. each trigger edge detector is selected individually by setting corresponding bits in capcon1. it s upports positive edge capture, negative edge capture, or any edge capture. each input capture channel has to set its own enabling bit capen0~2 (capcon0[6:4]) before use. i n p u t c a p t u r e i n t e r r u p t c a p f 0 c a p f 1 c a p f 2 t f 2 t i m e r 2 i n t e r r u p t p r e - s c a l a r f s y s r c m p 2 h t 2 d i v [ 2 : 0 ] ( t 2 m o d [ 6 : 4 ] ) r c m p 2 l t h 2 t l 2 t r 2 ( t 2 c o n . 2 ) t i m e r 2 m o d u l e c m p c r ( t 2 m o d . 2 ) c l e a r t i m e r 2 = c 0 h c 0 l n o i s e f i l t e r e n f 0 ( c a p c o n 2 . 4 ) o r [ 0 0 ] [ 0 1 ] [ 1 0 ] c a p 0 l s [ 1 : 0 ] ( c a p c o n 1 [ 1 : 0 ] ) c a p e n 0 ( c a p c o n 0 . 4 ) c a p f 0 i n p u t c a p t u r e 0 m o d u l e i n p u t c a p t u r e 1 m o d u l e i n p u t c a p t u r e 2 m o d u l e c a p 0 c a p 1 c a p 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 p 1 . 5 / i c 7 p 0 . 5 / i c 6 p 0 . 3 / i c 5 p 0 . 1 / i c 4 p 0 . 0 / i c 3 p 1 . 0 / i c 2 p 1 . 1 / i c 1 p 1 . 2 / i c 0 1 0 0 0 p 0 . 4 / i c 3
N76E003 datasheet jun 26 , 201 7 page 105 of 267 rev. 1.02 while input capture channel is enabled and the selected edge trigger occurs, the conte nt of the free running timer 2 counter, th2 and tl2, will be captured, transferred, and stored into the capture registers cnh and cnl. the edge triggering also causes capfn (capcon0.n) set by hardware. the interrupt will also generate if the ecap (eie.2) a nd ea bit are both set. for three input capture flags share the same interrupt vector, user should check capfn to confirm which channel comes the input capture edge. these flags should be cleared by software. the bit capcr (capcon2.3) benefits the implemen t of period calculation. setting capcr makes the hardware clear timer 2 as 0000h automatically after the value of th2 and tl2 have been captured after an input capture edge event occurs. it eliminates the routine software overhead of writing 16 - bit counter or an arithmetic subtraction. capcon0 C input capture control 0 7 6 5 4 3 2 1 0 - capen2 capen1 capen0 - capf2 capf1 capf0 - r/w r/w r/w - r/w r/w r/w address: 92h reset value: 0000 0000b bit name description 6 capen2 input capture 2 enable 0 = input capture channel 2 disable d . 1 = input capture channel 2 enable d . 5 capen1 input capture 1 enable 0 = input capture channel 1 disable d . 1 = input capture channel 1 enable d . 4 capen0 input capture 0 enable 0 = input capture channel 0 disable d . 1 = input ca pture channel 0 enable d . 2 capf2 input capture 2 flag this bit is set by hardware if the determined edge of input capture 2 occurs. this bit should cleared by software. 1 capf1 input capture 1 flag this bit is set by hardware if the determined edge of in put capture 1 occurs. this bit should cleared by software. 0 capf0 input capture 0 flag this bit is set by hardware if the determined edge of input capture 0 occurs. this bit should cleared by software.
N76E003 datasheet jun 26 , 201 7 page 106 of 267 rev. 1.02 capcon1 C input capture control 1 7 6 5 4 3 2 1 0 - - cap2ls[1:0] cap1ls[1:0] cap0ls[1:0] - - r/w r/w r/w address: 93h reset value: 0000 0000b bit name description 5:4 cap2ls[1:0] input capture 2 level select 00 = falling edge. 01 = rising edge. 10 = either rising or falling edge. 11 = reserved. 3:2 c ap1ls[1:0] input capture 1 level select 00 = falling edge. 01 = rising edge. 10 = either rising or falling edge. 11 = reserved. 1:0 cap0ls[1:0] input capture 0 level select 00 = falling edge. 01 = rising edge. 10 = either rising or falling edge. 11 = rese rved. capcon2 C input capture control 2 7 6 5 4 3 2 1 0 - enf2 enf1 enf0 - - - - - r/w r/w r/w - - - - address: 94h reset value: 0000 0000b bit name description 6 enf2 enable noise filer on input capture 2 0 = n oise filter on input capture channel 2 d isable d . 1 = n oise filter on input capture channel 2 enable d . 5 enf1 enable noise filer on input capture 1 0 = n oise filter on input capture channel 1 disable d . 1 = n oise filter on input capture channel 1 enable d . 4 enf0 enable noise filer on input captu re 0 0 = n oise filter on input capture channel 0 disable d . 1 = n oise filter on input capture channel 0 enable d . c0l C capture 0 low byte 7 6 5 4 3 2 1 0 c0l[7:0] r/w address: e4h reset value: 0000 0000b bit name description 7:0 c0l[7:0] input capture 0 result low byte the c0l register is the low byte of the 16 - bit result captured by input capture 0 .
N76E003 datasheet jun 26 , 201 7 page 107 of 267 rev. 1.02 c0h C capture 0 high byte 7 6 5 4 3 2 1 0 c0h[7:0] r/w address: e5h reset value: 0000 0000b bit name description 7:0 c0h[7:0] input capture 0 result h igh byte the c0h register is the high byte of the 16 - bit result captured by input capture 0 . c1l C capture 1 low byte 7 6 5 4 3 2 1 0 c1l[7:0] r/w address: e6h reset value: 0000 0000b bit name description 7:0 c1l[7:0] input capture 1 result low byte t he c1l register is the low byte of the 16 - bit result captured by input capture 1 . c1h C capture 1 high byte 7 6 5 4 3 2 1 0 c1h[7:0] r/w address: e7h reset value: 0000 0000b bit name description 7:0 c1h[7:0] input capture 1 result high byte the c1h re gister is the high byte of the 16 - bit result captured by input capture 1 . c2l C capture 2 low byte 7 6 5 4 3 2 1 0 c2l[7:0] r/w address: edh reset value: 0000 0000b bit name description 7:0 c2l[7:0] input capture 2 result low byte the c2l register is the low byte of the 16 - bit result captured by input capture 2.
N76E003 datasheet jun 26 , 201 7 page 108 of 267 rev. 1.02 c2h C capture 2 high byte 7 6 5 4 3 2 1 0 c2h[7:0] r/w address: eeh reset value: 0000 0000b bit name description 7:0 c2h[7:0] input capture 2 result high byte the c2h register is the high byte of the 16 - bit result captured by input capture 2 . capcon 3 C input capture control 3 7 6 5 4 3 2 1 0 cap13 cap12 cap11 cap10 cap03 cap02 cap01 cap00 r/w r/w r/w r/w r/w r/w r/w r/w address: f1 h reset value: 0000 0000b bit name description [7:4] c ap1[3:0] input capture channel 1 input pin select 0 00 0 = p1.2/ic0 0 0 0 1 = p1.1/ic1 00 10 = p1.0/ic2 00 11 = p0.0/ic3 0100 = p0.4/ic3 0101 = p0.1/ic4 0110 = p0.3/ic5 0111 = p0.5/ic6 1000 = p1.5/ic7 others = p1.2/ic0 [3:0] cap0[3:0] input capture channel 0 inp ut pin select 0 00 0 = p1.2/ic0 0 0 0 1 = p1.1/ic1 00 10 = p1.0/ic2 00 11 = p0.0/ic3 0100 = p0.4/ic3 0101 = p0.1/ic4 0110 = p0.3/ic5 0111 = p0.5/ic6 1000 = p1.5/ic7 others = p1.2/ic0
N76E003 datasheet jun 26 , 201 7 page 109 of 267 rev. 1.02 capcon 4 C input capture control 4 7 6 5 4 3 2 1 0 - - - - cap23 cap22 cap21 ca p20 - - - - r/w r/w r/w r/w address: f2 h reset value: 0000 0000b bit name description [3:0] cap2[3:0] input capture channel 2 input pin select 0 00 0 = p1.2/ic0 0 0 0 1 = p1.1/ic1 00 10 = p1.0/ic2 00 11 = p0.0/ic3 0100 = p0.4/ic3 0101 = p0.1/ic4 0110 = p0.3/ic 5 0111 = p0.5/ic6 1000 = p1.5/ic7 others = p1.2/ic0
N76E003 datasheet jun 26 , 201 7 page 110 of 267 rev. 1.02 10. timer 3 timer 3 is implemented simply as a 16 - bit auto - reload, up - counting timer. the user can select the pre - scale with t3ps[2:0] (t3con[2:0]) and fill the reload value into r h3 and r l3 registers t o determine its overflow rate. user then can set tr3 (t3con.3) to start counting. when the counter rolls over ffffh, tf3 (t3con.4) is set as 1 and a reload is generated and causes the contents of the r h3 and r l3 registers to be reloaded into the internal 1 6 - bit counter. if et3 (eie 1 . 1 ) is set as 1, timer 3 interrupt service routine will be served. tf3 is auto - cleared by hardware after entering its interrupt service routine. timer 3 can also be the baud rate clock source of both uart s . for details, please se e section 13.5 baud rat e on page 127 . figure 10 - 1 . timer 3 block diagram t3con C timer 3 control 7 6 5 4 3 2 1 0 smod _ 1 smod0 _ 1 brck tf3 tr3 t3ps[2:0] r/w r/w r/w r/w r/w r/w address: c4h , page:0 reset value: 0000 0000b bit name description 4 tf3 timer 3 overflow flag this bit is set when timer 3 overflows. it is automatically cleared by hardware when the program executes the timer 3 interrupt service routine. this bit can be set or cleared by software. 3 tr3 timer 3 run control 0 = timer 3 is halted. 1 = timer 3 starts running. note that the reload registers rh3 and rl3 can only be written when timer 3 is halted (tr3 bit is 0). if any of rh3 or rl3 is written if tr3 is 1, result is unpredictable. r l 3 t r 3 ( t 3 c o n . 3 ) f s y s i n t e r n a l 1 6 - b i t c o u n t e r 0 7 r h 3 0 7 t i m e r 3 o v e r f l o w p r e - s c a l a r ( 1 / 1 ~ 1 / 1 2 8 ) t 3 p s [ 2 : 0 ] ( t 3 c o n [ 2 : 0 ] ) t f 3 ( t 3 c o n . 4 ) t i m e r 3 i n t e r r u p t
N76E003 datasheet jun 26 , 201 7 page 111 of 267 rev. 1.02 bit name description 2:0 t3ps[2:0] timer 3 pre - scalar these bits determine the scale of the clock divider for timer 3. 000 = 1/1. 001 = 1/2. 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. rl3 C timer 3 reload low byte 7 6 5 4 3 2 1 0 rl3[7:0] r/w address: c5h , page:0 reset value: 0000 0000b bit name description 7:0 rl3[7:0] timer 3 reload low byte i t holds the low byte of the reload value of timer 3 . rh3 C timer 3 reload high byte 7 6 5 4 3 2 1 0 rh3[7:0] r/w address: c6h , page:0 reset value: 0000 0000b bit name description 7:0 rh3[7:0] timer 3 reload high byte i t holds the high byte of the reload value of time 3 .
N76E003 datasheet jun 26 , 201 7 page 112 of 267 rev. 1.02 11. watchdog timer (wdt) the N76E003 provides one watchdog timer (wdt) . it can be configured as a time - out reset timer to reset whole device. once the device runs in an abnormal status or hangs up by outward interference, a wdt reset recover the sys tem . it provides a system monitor, which improves the reliability of the system. therefore, wdt is especially useful for system that is susceptible to noise, power glitches, or electrostatic discharge. the wdt also can be configured as a general purpose ti mer, of which t he periodic interrupt serve s as an event timer or a durational system supervisor in a monitoring system , which is able to operate during idle or power - down mode. wdten[3:0] (config4[7:4]) initialize the wdt to operate as a time - out reset tim er or a general purpose timer. config4 7 6 5 4 3 2 1 0 wdten[3:0] - - - - r/w - - - - factory default value: 1111 1111b bit name description 7:4 wdten[3:0] wdt enable this field configures the wdt behavior after mcu execution. 1 111 = wdt is disabled. wdt can be used as a general purpose timer via software control. 0101 = wdt is enabled as a time - out reset timer and it stops running during idle or power - down mode . others = wdt is enabled as a time - out reset timer and it keeps running during idle or powe r - down mode . the wdt is implemented with a set of divider that divides the low - speed internal oscillator clock nominal 10 khz . the divider output is selectable and determines the time - out interval. when the time - out interval is fulfilled, it will wake th e system up from idle or power - down mode and an interrupt event will occur if wdt interrupt is enabled . if wdt is initialized as a time - out reset timer , a system reset will occur after a period of delay if without any software action . wdcon C watchdog time r control ( ta protected ) 7 6 5 4 3 2 1 0 wdtr wdclr wdtf widpd wdtrf [ 1 ] wdps[2:0] [ 2 ] r/w r/w r/w r/w r/w r/w address: aah reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7 wdtr wdt run this bit is valid only when control bits in wdten[3:0] (config4[7:4]) are all 1. at this time, wdt works as a general purpose timer. 0 = wdt disable d . 1 = wdt enabled. the wdt counter starts running.
N76E003 datasheet jun 26 , 201 7 page 113 of 267 rev. 1.02 bit name description 6 wdclr wdt clear setting this bit will reset the wdt count to 00h. it puts the counter in a known state and prohibit the system from unpredictable reset. the meaning of writing and reading wdclr bit is different. writing: 0 = no effect. 1 = clearing wdt counter. reading: 0 = wdt counter is complet ely cleared. 1 = wdt counter is not yet cleared. 5 wdtf wdt time - out flag this bit indicates an overflow of wdt counter. this flag should be cleared by software. 4 widpd wdt running in idle or power - down mode this bit is valid only when control bits in wdten[3:0] (config4[7:4]) are all 1. it decides whether wdt runs in idle or power - down mode when wdt works as a general purpose timer. 0 = wdt stops running during idle or power - down mode. 1 = wdt keeps running during idle or power - down mode. 3 wdtrf wdt reset flag when the cpu is reset by wdt time - out event, this bit will be set via hardware. this flag is recommended to be cleared via software after reset. 2:0 wdps[2:0] wdt clock pre - scalar select these bits determine the pre - scale of wdt clock from 1/1 through 1/256. see table 11 - 1 . the default is the maximum pre - scale value. [1] wdtrf will be cleared after power - on reset, be set after wdt reset, and remains unchanged after any other resets. [2] wdps[2:0] are al l set after power - on reset and keep unchanged after any reset other than power - on reset. the watchdog time - out interval is determined by the formula , where f lirc is the frequency of internal 10 khz oscillator. the following table sh ows an example of the watchdog time - out interval with different pre - scales. 64 scalar divider clock f 1 lirc
N76E003 datasheet jun 26 , 201 7 page 114 of 267 rev. 1.02 table 11 - 1 . watchdog timer - out interval u nder d ifferent p re - scalars w d ps . 2 w d ps . 1 w d ps . 0 clock divider s cal e watchdog time - out interv al ( f lirc ~ = 10 khz ) 0 0 0 1/1 6.40 ms 0 0 1 1/4 25.60 ms 0 1 0 1/8 51.20 ms 0 1 1 1/16 102.40 ms 1 0 0 1/32 204.80 ms 1 0 1 1/64 409.60 ms 1 1 0 1/128 819.20 ms 1 1 1 1/256 1.638 s 11.1 time - out r eset t imer when the config bits wdten [3:0] (config4[7:4]) is not fh, the wdt is initialized as a time - out reset timer. if wdten[3:0] is not 5h, the wdt is allowed to continue running after the system enters idle or power - down mode. note that when wdt is initialized as a time - out reset timer, wdtr and widpd has no function. figure 11 - 1 . wdt as a time - out res e t timer after the device is powered and it starts to execute software code , the wdt starts counting simultaneo usly . the time - out interval is selected by the three bits w d ps [2: 0 ] ( wdcon [2:0]). when the selected time - out occurs, the wdt will set the interrupt flag wdtf ( wdcon .5). if t he wdt interrupt enable bit ewdt ( eie.4 ) and global interrupt enable ea are both se t, the wdt interrupt routine will be executed . meanwhile, a n additional 512 clocks of the low - speed internal oscillator delays to expect a counter clearing by setting wdclr to avoid the system reset by wdt if the device operates normally . if no counter res et by writing 1 to wdclr during this 512 - clock period, a wdt reset will happen. setting wdclr bit is used to clear the counter of the wdt . this bit is self - cleared for user monitoring it. once a reset due to wdt occurs, the wdt reset flag wdtrf ( wdcon .3) w ill f l i r c w d c l r w d p s [ 2 : 0 ] w d t c o u n t e r ( 6 - b i t ) c l e a r o v e r f l o w w d t r e s e t 5 1 2 - c l o c k d e l a y 1 0 k h z i n t e r n a l o s c i l l a t o r w d t r f w d t f w d t i n t e r r u p t c l e a r p r e - s c a l a r ( 1 / 1 ~ 1 / 2 5 6 )
N76E003 datasheet jun 26 , 201 7 page 115 of 267 rev. 1.02 be set. this bit keeps unchanged after any reset other than a power - on reset. user may clear wdtrf via software. note that all bits in wdcon require timed access writing. notice : wdt counter has been specially taken care. the hardware automatically cle ars wdt counter and pre - scalar value after : (1) e ntering into or being woken - up from idle or power down mode (2) a ny resets . it prevents unconscious system reset. the main application of the wdt with time - out reset enabling is for the system monitor. this is important in real - time control applications. in case of some power glitches or electro - magnetic interference, cpu may begin to execute erroneous codes and operate in an unpredictable state. if this is left unchecked the entire system may crash. using t he wdt during software development requires user to select proper feeding dog time by clearing the wd counter. by inserting the instruction of setting wdclr, it allows the code to run without any wdt reset. however if any erroneous code executes by any interference, the instructions to clear the wdt counter will not be executed at the required instants. thus the wdt reset will occur to reset the system state from an erroneously executing condition and recover the system. 11.2 general purpose timer there is an other application of the wdt, which is used as a simple, long period timer. when the config bits wdten[3:0] (config4[7:4]) is fh, the wdt is initialized as a general purpose timer. in this mode, wdtr and widpd are fully accessed via software. figure 11 - 2 . watchdog timer block diagram the wdt starts running by setting wdtr as 1 and halts by clearing wdtr as 0. the wdtf flag will be set while the wdt completes the selected time inte rval. the software polls the wdtf flag to detect a time - out. a n interrupt will occur if the individual interrupt ewdt (eie.4) and global interrupt enable ea is set. wdt will continue counting. user should clear wdtf and wait for the next overflow by pollin g wdtf flag or waiting for the interrupt occurrence. in some application of low power consumption, the cpu usually stays in idle mode when nothing needs to be served to save power consumption. after a while the cpu will be woken up to check if f l i r c i d l ( p c o n . 0 ) p d ( p c o n . 1 ) w i d p d w d t r w d c l r w d p s [ 2 : 0 ] w d t c o u n t e r ( 6 - b i t ) c l e a r o v e r f l o w 1 0 k h z i n t e r n a l o s c i l l a t o r w d t f w d t i n t e r r u p t p r e - s c a l a r ( 1 / 1 ~ 1 / 2 5 6 )
N76E003 datasheet jun 26 , 201 7 page 116 of 267 rev. 1.02 anything nee ds to be served at an interval of programmed period implemented by timer 0 ~3 . however, the current consumption of dle mode still keeps at a ma level. o further reducing the current consumption to ma level, the pu should stay in power - down mode when nothing needs to be served, and has the ability of waking up at a programmable interval. the N76E003 is equipped with this useful function by wdt waking up. it provides a very low power internal oscillator 10 khz as the clock source of the wdt . it is also able to count under power - down mode and wake cpu up. the demo code to accomplish this feature is shown below. for example: org 0000h ljmp start org 00 53 h ljmp w dt _ isr org 0100h ;******************************************************************** ; w dt interrupt service routine ;******************************************************************** w dt _ isr: clr ea mov ta,#0aah mov ta,#55h anl wdcon ,#11011111b ; c lear wdt interrupt flag setb ea reti ;************************************************ ******************** ; start here ;******************************************************************** start: mov ta,#0aah mov ta,#55h orl wdcon ,#000 10 111b ;choose interval length and enable wdt running during ; power - down setb ewdt ; e nable wdt i nterrupt setb ea mov ta,#0aah mov ta,#55h orl wdcon ,#10000000b ; wdt run ;******************************************************************** ;enter power - down m od e ;******************************************************************** loop: orl pco n,#02h ljmp loop
N76E003 datasheet jun 26 , 201 7 page 117 of 267 rev. 1.02 12. self wake - up timer (wkt) the N76E003 has a dedicated s elf wake - u p t imer (wkt), which serves for a periodic wake - up timer in low power mode or for general purpose timer. wkt remains counting in idle or power - down mode. when wkt is being us ed as a wake - up timer, a start of wkt can occur just prior to entering a power management mode. wkt has one clock source, internal 10 khz . note that the system clock frequency must be twice over wkt clock. if wkt starts counting, the selected clock source will remain active once the device enters idle or power - down mode. note that the selected clock source of wkt will not automatically enabled along with wkt configuration. user should manually enable the selected clock source and waiting for stability to en sure a proper operation. the wkt is implemented simply as a 8 - bit auto - reload, up - counting timer with pre - scale 1/1 to 1/ 2048 selected by wkps[2:0] (wkcon[2:0]). user fills the reload value into rwk register to determine its overflow rate. the wktr ( wk con. 3) can be set to start counting . when the counter rolls over ffh, wktf ( wk con.4) is set as 1 and a reload is generated and causes the contents of the rwk register to be reloaded into the internal 8 - bit counter. if e wkt (eie1. 2 ) is set as 1, wkt interrupt s ervice routine will be served. figure 12 - 1 . self wake u p timer block diagram w k con C self wake - u p timer control 7 6 5 4 3 2 1 0 - - - wktf wktr wkps[2:0] - - - r/w r/w r/w ad dress: 8f h reset value: 0000 0000b bit name description 5 - reserved 4 wktf wkt overflow flag this bit is set when wkt overflows. if the wkt interrupt and the global interrupt are enable d , setting this bit will make cpu execute wkt interrupt service rout ine. this bit is not automatically cleared via hardware and should be cleared via software. w k t r ( w k c o n . 3 ) i n t e r n a l 8 - b i t c o u n t e r r w k 0 7 w k t o v e r f l o w p r e - s c a l a r ( 1 / 1 ~ 1 / 2 0 4 8 ) w k p s [ 2 : 0 ] ( w k c o n [ 2 : 0 ] ) w k t f ( w k c o n . 4 ) w k t i n t e r r u p t 1 0 k h z i n t e r n a l o s c i l l a t o r f l i r c w k t c k ( w k c o n . 5 )
N76E003 datasheet jun 26 , 201 7 page 118 of 267 rev. 1.02 bit name description 3 wktr wkt run control 0 = wkt is halted. 1 = wkt starts running. note that the reload register rwk can only be written when wkt is halted ( wktr bit is 0). if wkt is written while wktr is 1, result is unpredictable. 2:0 wk ps[2:0] wkt pre - scalar these bits determine the pre - scale of wkt clock . 000 = 1/1. 001 = 1/ 4 . 010 = 1/ 16 . 011 = 1/ 64 . 100 = 1/ 256 . 101 = 1/ 512 . 110 = 1/ 1024 . 111 = 1/ 2048 . rwk C self wake - u p time r reload byte 7 6 5 4 3 2 1 0 rwk [7:0] r/w address: 86 h reset value: 0000 0000b bit name description 7:0 rwk [7:0] wkt reload byte i t holds the 8 - bit reload value of wkt . note that rwk should not be ffh if the pre - scale is 1/1 for implement limitation.
N76E003 datasheet jun 26 , 201 7 page 119 of 267 rev. 1.02 13. serial port (uart) the N76E003 includes two enhanced full duplex serial port s enhanced with automatic address recognition and framing error detection. as control bits of these two serial ports are implemented the same, the bit names (including interrupt e nabling or priority setting bits) end with _ (e.g. o _ 1) to indicate serial port 1 control bits for making a distinction between these two serial ports. generally speaking, in the following contents, there will not be any reference to serial port 1, b ut only to serial port 0 . each serial port supports one synchronous communication mode, mode 0, and three modes of full duplex uart (universal asynchronous receiver and transmitter), mode 1, 2, and 3. this means it can transmit and receive simultaneously. the serial port is also receiving - buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. the receiving and transmitting registers are both accessed at sbuf. writing to sbuf loads the transmitting register, and reading sbuf accesses a physically separate receiving register. there are four operation modes in serial port. in all four modes, transmission initiates by any instruction that uses sbuf as a destination register. note that befor e serial port function works, the port latch bits of p 0 . 7 and p0. 6 (for rxd and txd pins) or p 0 . 2 and p 1 . 6 (for rxd_1 and txd_1 pins) have to be set to 1. for application flexibility, txd and rxd pins of serial port 0 can be exchanged by uart0px (auxr1. 2 ) . scon C serial port control ( bit - addressable ) 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri r/w r/w r/w r/w r/w r/w r/w r/w address: 98h reset value : 0000 0000b bit name description 7 sm0/fe serial port mode select smod0 (pcon.6) = 0: see table 13 - 1 . serial port 0 mode description for details. smod0 (pcon.6) = 1: sm0/fe bit is used as frame error (fe) status flag. it is cleared by software. 0 = frame error (fe) did not occur. 1 = frame error (fe) occurred a nd detected. 6 sm1
N76E003 datasheet jun 26 , 201 7 page 120 of 267 rev. 1.02 bit name description 5 sm2 multiproc essor communication mode enable the function of this bit is dependent on the serial port 0 mode. mode 0: this bit select the baud rate between f sys /12 and f sys / 2 . 0 = the clock runs at f sys /12 baud rate. it maintains s tandard 8051 compatibility. 1 = the clock runs at f sys / 2 baud rate for faster serial communica - tion. mode 1: this bit checks valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is valid only when the r eceived stop bit is logic 1 and the received data matches given or broadcast address. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9 th bit. 1 = reception is valid only when the receiv ed 9 th bit is logic 1 and the received data matches given or broadcast address. 4 ren receiving enable 0 = serial port 0 reception d isabled. 1 = serial port 0 reception e nabled in mode 1,2, or 3. in mode 0, reception is initiated by the condition re n = 1 and ri = 0. 3 tb8 9 th transmitted bit this bit defines the state of the 9 th transmission bit in serial port 0 mode 2 or 3. it is not used in mode 0 or 1. 2 rb8 9 th received bit the bit identifies the logic level of the 9 th received bit in serial po rt 0 mode 2 or 3. in mode 1, rb8 is the logic level of the received stop bit. sm2 bit as logic 1 has restriction for exception. rb8 is not used in mode 0. 1 ti transmission interrupt flag this flag is set by hardware when a data frame has been transmitte d by the serial port 0 after the 8 th bit in mode 0 or the last data bit in other modes. when the serial port 0 interrupt is enabled, setting this bit causes the cpu to execute the serial port 0 interrupt service routine. this bit should be cleared manually via software. 0 ri receiving interrupt flag this flag is set via hardware when a data frame has been received by the serial port 0 after the 8 th bit in mode 0 or after sampling the stop bit in mode 1, 2, or 3. sm2 bit as logic 1 has restriction for excep tion. when the serial port 0 interrupt is enabled, setting this bit causes the cpu to execute to the serial port 0 interrupt service routine. this bit should be cleared manually via software.
N76E003 datasheet jun 26 , 201 7 page 121 of 267 rev. 1.02 scon _ 1 C serial port 1 control (bit - addressable) 7 6 5 4 3 2 1 0 sm0 _ 1/fe _ 1 sm1 _ 1 sm2 _ 1 ren _ 1 tb8 _ 1 rb8 _ 1 ti _ 1 ri _ 1 r/w r/w r/w r/w r/w r/w r/w r/w address: f 8h reset value: 0000 0000b bit name description 7 sm0 _ 1/fe _ 1 serial port 1 mode select smod0 _ 1 (t3con.6) = 0: see table 13 - 2 . serial port 1 mode description for details. smod0 _ 1 (t3con.6) = 1: sm0 _ 1/fe _ 1 bit is used as frame error (fe) status flag. it is cleared by software. 0 = frame error (fe) did not occur. 1 = frame error (fe) occur red and detected. 6 sm1 _ 1 5 sm2 _ 1 multiproc essor communication mode enable the function of this bit is dependent on the serial port 1 mode. mode 0: no effect. mode 1: this bit checks valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is valid only when the received stop bit is logic 1 and the received data matches given or broadcast address. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9 th bit. 1 = reception is val id only when the received 9 th bit is logic 1 and the received data matches given or broadcast address. 4 ren _ 1 receiving enable 0 = serial port 1 reception d isabled. 1 = serial port 1 reception e nabled in mode 1,2, or 3. in mode 0, reception is init iated by the condition ren_1 = 1 and ri_1 = 0. 3 tb8 _ 1 9 th transmitted bit this bit defines the state of the 9 th transmission bit in serial port 1 mode 2 or 3. it is not used in mode 0 or 1. 2 rb8 _ 1 9 th received bit the bit identifies the logic level of the 9 th received bit in serial port 1 mode 2 or 3. in mode 1, rb8 _ 1 is the logic level of the received stop bit. sm2 _ 1 bit as logic 1 has restriction for exception. rb8 _ 1 is not used in mode 0. 1 ti _ 1 transmission interrupt flag this flag is set by hardw are when a data frame has been transmitted by the serial port 1 after the 8 th bit in mode 0 or the last data bit in other modes. when the serial port 1 interrupt is enabled, setting this bit causes the cpu to execute the serial port 1 interrupt service rou tine. this bit must be cleared manually via software.
N76E003 datasheet jun 26 , 201 7 page 122 of 267 rev. 1.02 bit name description 0 ri _ 1 receiving interrupt flag this flag is set via hardware when a data frame has been received by the serial port 1 after the 8 th bit in mode 0 or after sampling the stop bit in mode 1, 2, or 3. sm2 _ 1 bit as logic 1 has restriction for exception. when the serial port 1 interrupt is enabled, setting this bit causes the cpu to execute to the serial port 1 interrupt service routine. this bit must be cleared manually via software. pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value : see table 6 - 2 . sfr definitions and reset values bit name description 7 smod serial port 0 double baud rate enable setting this bit doubles the serial port baud rate when uart0 is in mode 2 or when timer 1 overflow is used as the baud rate source of uart0 mode 1 or 3. see table 13 - 1 . serial port 0 mode description for de tails. 6 smod0 serial port 0 framing error flag access enable 0 = scon.7 accesses to sm0 bit. 1 = scon.7 accesses to fe bit. t3con C timer 3 control 7 6 5 4 3 2 1 0 smod _ 1 smod0 _ 1 brck tf3 tr3 t3ps[2:0] r/w r/w r/w r/w r/w r/w address: c4h , page:0 res et value: 0000 0000b bit name description 7 smod _ 1 serial port 1 double baud rate enable setting this bit doubles the serial port baud rate when uart1 is in mode 2. see table 13 - 2 . serial port 1 mode description f or details. 6 smod0 _ 1 serial port 1 framing error access enable 0 = scon_1.7 accesses to sm0_1 bit. 1 = scon_1.7 accesses to fe_1 bit. table 13 - 1 . serial port 0 mode description mode sm0 sm1 description fra me bits baud rate 0 0 0 synchronous 8 f sys divided by 12 or by 2 [1] 1 0 1 asynchronous 10 timer 1 /timer 3 overflow rate divided by 32 or 16 [ 2 ] 2 1 0 asynchronous 11 f sys divided by 32 or 64 [ 2 ] 3 1 1 asynchronous 11 timer 1 /timer 3 overflow rate divided by 32 or 16 [ 2 ] [1] while sm2 (scon.5) is logic 1. [2] while smod (pcon.7) is logic 1.
N76E003 datasheet jun 26 , 201 7 page 123 of 267 rev. 1.02 table 13 - 2 . serial port 1 mode description mode sm0 sm1 description frame bits baud rate 0 0 0 synchronous 8 f sys divide d by 12 or by 2 [1] 1 0 1 asynchronous 10 timer 3 overflow rate divided by 16 2 1 0 asynchronous 11 f sys divided by 32 or 64 [ 2 ] 3 1 1 asynchronous 11 timer 3 overflow rate divided by 16 [1] while sm2_1 (scon_1.5) is logic 1. [2] while smod_1 (t3con.7) i s logic 1. sbuf C serial port 0 data buffer 7 6 5 4 3 2 1 0 sbuf[7:0] r/w address: 99h reset value : 0000 0000b bit name description 7:0 sbuf[7:0] serial port 0 data buffer this byte actually consists two separate registers. one is the receiving resist er, and the other is the transmitting buffer. when data is moved to sbuf, it goes to the transmitting buffer and is shifted for serial transmission. when data is moved from sbuf, it comes from the receiving register. the transmission is initiated through g iving data to sbuf. sbuf_1 C serial port 1 data buffer 7 6 5 4 3 2 1 0 sbuf _ 1[7:0] r/w address: 9ah reset value: 0000 0000b bit name description 7:0 sbuf _ 1[7:0] serial port 1 data buffer this byte actually consists two separate registers. one is the r eceiving resister, and the other is the transmitting buffer. when data is moved to sbuf _1 , it goes to the transmitting buffer and is shifted for serial transmission. when data is moved from sbuf _1 , it comes from the receiving register. the transmission is initiated through giving data to sbuf _1 .
N76E003 datasheet jun 26 , 201 7 page 124 of 267 rev. 1.02 auxr1 C auxiliary register 1 7 6 5 4 3 2 1 0 swrf rstpinf hardf - gf2 uart0px 0 dps r/w r/w r/w - r/w r/w r r/w address: a2 h reset value : see table 6 - 2 . sfr definitions and reset values bit name description 2 uart0px serial port 0 pin exchange 0 = assign rxd to p0 .7 and txd to p0. 6 b y default. 1 = exchange rxd to p0. 6 and txd to p 0 . 7 . note that txd and rxd will exchange immediately once setting or clearing this bit. user should take care of not exchanging pins during transmission or receiving. or it may cause unpredictable situation and no warning alarms. 13.1 mode 0 mode 0 provides synchronous communication with external devices. serial data enters and exits through rxd pin. txd outputs the shift clocks. 8 - bit frame of data are transmitted or received. mode 0 therefore provides half - duplex communication because the transmitting or receiving data is via the same data line rxd. the baud rate is enhanced to be selected as f sys /1 2 if sm2 (scon.5) is 0 or as f sys / 2 if sm2 is 1 . note that whenever transmitting or receiving, the serial clock is always generated by the mcu . thus any device on the serial port in mode 0 should accept the mcu as the master. figure 13 - 1 shows the associated timing of the serial port in mode 0. figure 13 - 1 . serial port mode 0 timing diagram as shown there is one bi - directional data line (rxd) and one shift clock lin e (txd). the shift clocks are used to shift data in or out of the serial port controller bit by bit for a serial communication. data bits enter or emit lsb first. the band rate is equal to the shift clock frequency.
N76E003 datasheet jun 26 , 201 7 page 125 of 267 rev. 1.02 transmission is initiated by any instruc tion writes to sbuf. the control block will then shift out the clocks and begin to transfer data until all 8 bits are complete. then the transmitted flag ti (scon.1) will be set 1 to indicate one byte transmitting complete. reception is initiated by the co ndition ren (scon.4) = 1 and ri (scon.0) = 0. this condition tells the serial port controller that there is data to be shifted in. this process will continue until 8 bits have been received. then the received flag ri will be set as 1. user can clear ri to triggering the next byte reception. 13.2 mode 1 mode 1 supports asynchronous, full duplex serial communication. the asynchronous mode is commonly used for communication with pcs, modems or other similar interfaces. in mode 1, 10 bits are transmitted through txd or received through rxd including a start bit (logic 0), 8 data bits (lsb first) and a stop bit (logic 1). the baud rate is determined by the timer 1 . smod (pcon.7) setti ng 1 makes the baud rate double . figure 13 - 2 shows the associated timings of the serial port in mode 1 for transmitting and receiving. figure 13 - 2 . serial port mode 1 timing diagram transmission is initiated by any writing instructions to sbuf. tra nsmission takes place on txd pin. first the start bit comes out, the 8 - bit data follows to be shifted out and then ends with a stop bit. after the stop bit appears, ti (scon.1) will be set to indicate one byte transmission complete. all bits are shifted ou t depending on the rate determined by the baud rate generator. once the baud rate generator is activated and ren (scon.4) is 1, the reception can begin at any time. reception is initiated by a detected 1 - to - 0 transition at rxd. data will be sampled and shi fted in
N76E003 datasheet jun 26 , 201 7 page 126 of 267 rev. 1.02 at the selected baud rate. in the midst of the stop bit, certain conditions should be met to load sbuf with the received data: 1. ri (scon.0) = 0, and 2. either sm2 (scon.5) = 0, or the received stop bit = 1 while sm2 = 1 and the received data matc hes given or broadcast address. (for enhancement function, see 13.7 multiprocessor commu nication and 13.8 automat ic address recognition .) if these conditions are met, then the sbuf will be loaded with the received data, the rb8 (scon.2) with stop bit, and ri will be set. if these conditions fail, there will be no data loa ded and ri will remain 0. after above receiving progress, the serial control will look forward another 1 - to - 0 transition on rxd pin to start next data reception. 13.3 mode 2 mode 2 supports asynchronous, full duplex serial communication. different from mode1, t here are 11 bits to be transmitted or received. they are a start bit (logic 0), 8 data bits (lsb first), a programmable 9 th bit tb8 or rb8 bit and a stop bit (logic 1). the most common use of 9 th bit is to put the parity bit in it or to label address or da ta frame for multiprocessor communication. the baud rate is fixed as 1/32 or 1/64 the system clock frequency depending on smod (pcon.7) bit . figure 13 - 3 shows the associated timings of the serial port in mode 2 for transmitting and receiving. figure 13 - 3 . serial port mode 2 and 3 timing diagram
N76E003 datasheet jun 26 , 201 7 page 127 of 267 rev. 1.02 transmission is initiated by any writing instructions to sbuf. transmission takes place on txd pin. first the start bit com es out, the 8 - bit data and bit tb8 (scon.3) follows to be shifted out and then ends with a stop bit. after the stop bit appears, ti will be set to indicate the transmission complete. while ren is set, the reception is allowed at any time. a falling edge of a start bit on rxd will initiate the reception progress. data will be sampled and shifted in at the selected baud rate. in the midst of the stop bit, certain conditions should be met to load sbuf with the received data: 1. ri (scon.0) = 0, and 2. either s m2 (scon.5) = 0, or the received 9 th bit = 1 while sm2 = 1 and the received data matches given or broadcast address. (for enhancement function, see 13.7 multiprocessor commu nication and 13.8 automat ic address recognition .) if these conditions are met, the sbuf will be loaded with the received data, the rb8(scon.2) with th e received 9 th bit and ri will be set. if these conditions fail, there will be no data loaded and ri will remain 0. after above receiving progress, the serial control will look forward another 1 - to - 0 transition on rxd pin to start next data reception. 13.4 mode 3 mode 3 has the same operation as mode 2, except its baud rate clock source uses timer 1 overflows as its baud rate clocks. see figure 13 - 3 fo r timing diagram of mode 3. it has no difference from mode 2. 13.5 baud rat e the baud rate source and speed for different modes of serial port is quite different from one another. all cases are listed in ta ble 13 - 3 . the user should calculate the baud rate according to their system configu ration. in mode 1 or 3, the baud rate clock source of uart 0 can be selected from timer 1 or timer 3 . user can select the baud rate clock source by brck ( t3 con. 5 ). for uart1, its baud rate clock comes only from time r 3 as its unique clock source.
N76E003 datasheet jun 26 , 201 7 page 128 of 267 rev. 1.02 t3con C ti mer 3 control 7 6 5 4 3 2 1 0 smod _ 1 smod0 _ 1 brck tf3 tr3 t3ps[2:0] r/w r/w r/w r/w r/w r/w address: c4h , page:0 reset value: 0000 0000b bit name description 5 brck seria l port 0 baud rate clock source this bit selects which timer is used as the baud r ate clock source when serial port 0 is in mode 1 or 3. 0 = timer 1 . 1 = timer 3. when using timer 1 as the baud rate clock source, n ote that the timer 1 interrupt should be disabled. timer 1 itself can be configured for either imer or ounter operat ion. it can be in any of its three running modes. however, in the most typical applications, it is configured for imer operation, in the auto - reload mode (mode 2). if using timer 3 as the baud rate generator, its interrupt should also be disabled .
N76E003 datasheet jun 26 , 201 7 page 129 of 267 rev. 1.02 ta ble 13 - 3 . uart baud rate formulas uart m ode baud r ate c lock s ource baud rate formula number 0 system clock or [1] 1 2 system clock or [ 2 ] 2 1 or 3 timer 1 ( o nly for uart0) [ 3 ] or [ 4 ] 3 timer 3 (for uart0) [ 5] 4 timer 3 (for uart1) [ 5] 5 [1] sm2 (scon.5) or sm2_1(scon_1.5) is se t as logic 1 . [2] smod (pcon.7) or smod_1(t3con.7) is set as logic 1. [ 3 ] timer 1 is configured as a timer in auto - reload mode (mode 2). [ 4 ] t1m (ckcon.4) is set as logic 1 . while smod is 1, th1 should not be ffh. [ 5 ] { r h3 , r l3 } in the formula means . while smod is 1 and pre - scale is 1/1, {rh3,rl3} should not be ffffh . important : since the limitation of baud rate generator , s uggest setting baud rate under 38400 when system timer base 16mhz hirc value. following show the baud rate value table show the deviation upper 38400 baud rate. hirc target baud rate rhx rlx rhx + rlx dec v alue actual baud rate error % 16mhz 2400 0x fe 0x 5f 65119 2398.081535 0.0 79% 4800 0x ff 0x 30 65328 4807.692308 - 0.16 0% 9600 0x ff 0x 98 65432 9615.384615 - 0.16 0% 19200 0x ff 0x cc 65484 19230.76923 - 0.16 0% 38400 0x ff 0x e6 65510 38461.53846 - 0.16 0% 57600 0x ff 0x ef 65519 58823.52941 - 2.12 4% 115200 0x ff 0x f7 6552 7 111111.1111 3.549 % note: rhx and rlx setting value base on baud rate formula 4 (smod =1) or 5 . but in most application the baud rate 115200 is a common setting value. so we provide a special function to modify hirc to 16.6mhz. then the deviation of baud rate will be reasonable . following table shows the error value when hirc and timer base modified . 12 / f sys 2 / f sys 64 / f sys 32 / f sys ( ) 1 th 256 12 f 32 2 sys smod - 1 th 256 f 32 2 sys smod - ( ) } 3 rl , 3 rh { 65536 scale e pr f 32 2 sys smod - - ( ) } 3 rl , 3 rh { 65536 scale e pr f 16 1 sys - - 3 rl + 3 rh 256
N76E003 datasheet jun 26 , 201 7 page 130 of 267 rev. 1.02 hirc target baud rate rhx rlx rhx + rlx dec v alue actual baud rate error % 16.6mhz 2400 0x fe 0x 50 65104 2401.62037 - 0.067 % 4800 0x ff 0x 28 65320 4803.240741 - 0.067 % 9600 0x ff 0x 94 65428 9606.481481 - 0.067 % 19200 0xf f 0x ca 65482 19212.96296 - 0.06 7 % 38400 0xf f 0x e5 65509 38425.92593 - 0.067 % 57600 0x ff 0x ee 65518 57638.88889 - 0.067 % 115200 0x ff 0x f7 65527 115277.7778 - 0.067 % note: rhx and rlx setting value base on baud rate formula 4 (smod =1) or 5 N76E003 provide two bytes sfr to user trim h irc value, default after reset the value is trim to 16mhz, once modify this sfr, the hirc value will change. suggest decrease reset value 15(dec.) will trim hirc to 16.6mhz. following two byte combine the 9 bit internal rc trim value. each bit deviation is 0.25% of 16mhz that means about 40khz / bit . rctrim 0 C high speed internal oscillator 16 mhz trim 0 7 6 5 4 3 2 1 0 hirctrim[8:1] r/w address: 84 h reset value: 16mhz hirc value rctrim 1 C high speed internal oscillator 16 mhz trim 1 7 6 5 4 3 2 1 0 - - - - - - - hirctrim.0 - - - - - - - r/w address: 85 h reset value: 16mhz hirc value following is the demo code to modify hirc to 16.6mhz, sfr rctrim0 = 0x84; sfr rctrim1 = 0x85; bit bit_tmp; #define set_iapen bit_tmp=ea;ea=0;ta=0xaa;ta=0x 55;chpcon|= set_bit0 ;ea=bit_tmp #define set_iapgo bit_tmp=ea;ea=0;ta=0xaa;ta=0x55;iaptrg|=set_bit0 ;ea=bit_tmp #define clr_iapen bit_tmp=ea;ea=0;ta=0xaa;ta=0x 55;chpcon&=~set_bit0;ea=bit_tmp unsigned char hircmap0,hircmap1; unsigned int trimvalue16bit; void modi fy_hirc_vlaue(void) { set_iapen; iapal = 0x30; iapah = 0x00; iapcn = read_uid; set_iapgo;
N76E003 datasheet jun 26 , 201 7 page 131 of 267 rev. 1.02 hircmap0 = iapfd; iapal = 0x31; iapah = 0x00; set_iapgo; hircmap1 = iapfd; clr_iapen; trimvalue16bit = ((hircmap0<<1)+(hircmap1&0x01)); trimvalue16bit = trimvalue16bit - 15; hircmap1 = trimvalue16bit&0x01; hircmap0 = trimvalue16bit>>1; ta=0xaa; ta=0x55; rctrim0 = hircmap0; ta=0xaa; ta=0x55; rctrim1 = hircmap1; } 13.6 framing error detection framing error detection is provided for async hronous modes. (mode 1, 2, or 3.) the framing error occurs when a valid stop bit is not detected due to the bus noise or contention. the uart can detect a framing error and notify the software. the framing error bit, fe, is located in scon.7. this bit norm ally serves as sm0. while the framing error accessing enable bit smod0 (pcon.6) is set 1, it serves as fe flag. actually, sm0 and fe locate in different registers. the fe bit will be set 1 via hardware while a framing error occurs. fe can be checked in uar t interrupt service routine if necessary. note that smod0 should be 1 while reading or writing to fe. if fe is set, any following frames received without frame error will not clear the fe flag. the clearing has to be done via software. 13.7 multiprocessor commu nication the N76E003 multiprocessor communication feature lets a master device send a multiple frame serial message to a slave device in a multi - slave configuration. it does this without interrupting other slave devices that may be on the same serial line. this feature can be used only in uart mode 2 or 3. user can enable this function by setting sm2 (scon.5) as logic 1 so that when a byte of frame is received, the serial interrupt will be generated only if the 9 th bit is 1. (for mode 2, the 9 th bit is the stop bit.) when the sm2 bit is 1, serial data frames that are received with the 9 th bit as 0 do not generate an interrupt. in this case, the 9 th bit simply separates the slave address from the serial data. when the master device wants to transmit a block o f data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. note that in this case, an address byte differs from a data byte. in an address byte, the 9 th bit is 1 and in a data byte, it is 0. the addre ss byte
N76E003 datasheet jun 26 , 201 7 page 132 of 267 rev. 1.02 interrupts all slaves so that each slave can examine the received byte and see if it is addressed by its own slave address. the addressed slave then clears its sm2 bit and prepares to receive incoming data bytes. the sm2 bits of slaves that were no t addressed remain set, and they continue operating normally while ignoring the incoming data bytes. follow the steps below to configure multiprocessor communications: 1. set all devices (masters and slaves) to uart mode 2 or 3. 2. write the sm2 bit of all the slave devices to 1. 3. the master device s transmission protocol is: C first byte: the address, identifying the target slave device, (9 th bit = 1). C next bytes: data, (9 th bit = 0). 4. when the target slave receives the first byte, all of the slaves are interrupted because the 9 th data bit is 1. the targeted slave compares the address byte to its own address and then clears its sm2 bit to receiving incoming data. the other slaves continue operating normally. 5. after all data bytes have been received, set sm2 back to 1 to wait for next address. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. for mode 1 reception, if sm2 is 1, the receiving interrupt will not be issue unless a valid stop bit is received. 13.8 automat ic address recognition the automatic address recognition is a feature , which enhances the multiprocessor communication feature by allowing the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feat ure saves a great deal of software overhead by eliminating the need for the software to examine every serial address , which passes by the serial port. only when the serial port recognizes its own address, the receiver sets ri bit to request an interrupt. t he automatic address recognition feature is enabled when the multiprocessor communication feature is enabled, sm2 is set. if desired, user may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place o f the ninth data bit. ri is set only when the received command frame address matches the devices address and is terminated by a valid stop bit.
N76E003 datasheet jun 26 , 201 7 page 133 of 267 rev. 1.02 using the automatic address recognition feature allows a master to selectively communicate with one or more sla ves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. wo f s are used to define the slave address, add , and the slave address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are dont care. he ade mask can be logically a ded with the add to create the given address , which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be r ecognized while excluding others. saddr C slave 0 address 7 6 5 4 3 2 1 0 saddr[7:0] r/w address: a9h reset value: 0000 0000b bit name description 7:0 saddr[7:0] slave 0 address his byte specifies the microcontrollers own slave address for uatr0 mult i - processor communication. saden C slave 0 address mask 7 6 5 4 3 2 1 0 saden[7:0] r/w address: b9h reset value : 0000 0000b bit name description 7:0 saden[7:0] slave 0 address mask this byte is a mask byte of uart0 that contains dont - care bits (de fined by zeros) to form the devices given address. the dont - care bits provide the flexibility to address one or more slaves at a time. saddr_1 C slave 1 address 7 6 5 4 3 2 1 0 saddr _ 1[7:0] r/w address: bbh reset value: 0000 0000b bit name descript ion 7:0 saddr _ 1[7:0] slave 1 address his byte specifies the microcontrollers own slave address for uart1 multi - processor communication.
N76E003 datasheet jun 26 , 201 7 page 134 of 267 rev. 1.02 saden_1 C slave 1 address mask 7 6 5 4 3 2 1 0 saden _ 1[7:0] r/w address: bah reset value: 0000 0000b bit name des cription 7:0 saden _ 1[7:0] slave 1 ad dress mask this byte is a mask byte of uart1 that contains dont - care bits (defined by zeros) to form the devices given address. the dont - care bits provide the flexibility to address one or more slaves at a time. the following examples will help to show the versatility of this scheme. example 1, slave 0: saddr = 11000000 b saden = 11111101 b given = 110000x0 b example 2, slave 1: saddr = 11000000 b saden = 11111110 b given = 1100000x b in the above example saddr is t he same and the saden data is used to differentiate between the two slaves. slave 0 requires 0 in bit 0 and it ignores bit 1. slave 1 requires 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires 0 in bit 1. a unique address for slave 1 would be 11000001b since 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address , which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 11000000 b as their broadcast address. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: example 1, slave 0: saddr = 11000000 b saden = 11111001 b given = 11000xx0 b example 2, slave 1: saddr = 11100000 b saden = 11111010 b given = 11100x0x b
N76E003 datasheet jun 26 , 201 7 page 135 of 267 rev. 1.02 example 3, slave 2: saddr = 11000000 b saden = 11111100 b given = 110000xx b in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addre ssed by 11100110b. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 11100101b. slave 2 requires that bit 2 = 0 and its unique address is 11100011b. to select slaves 0 and 1 and exclude slave 2 use address 11100100b, since it is necessary to make bit 2 = 1 to exclude slave 2. he broadcast address for each slave is created by taking the logical o of add and ade . zeros in this result are treated as dont - cares, e.g.: saddr = 01010110b saden = 11111100b broadcast = 1111111 x b he use of dont - care bits provides flexibility in defining the broadcast address, however in most applications, interpreting the dont - cares as all ones, the broadcast address will be ffh. on reset, saddr and saden are initialized to 00h. this produce s a given address of all dont cares as well as a broadcast address of all xxxxxxxxb (all dont care bits). his ensures that the serial port will reply to any addr ess, and so that it is backwards compatible with the standard 80c51 microcontrollers that do not support automatic address recognition.
N76E003 datasheet jun 26 , 201 7 page 136 of 267 rev. 1.02 14. serial peripheral in terface (spi) the N76E003 provides a serial peripheral interface (spi) block to support high - speed serial communication. spi is a full - duplex, high - speed , synchronous communication bus between microcontroller s or other peripheral devices such as serial eeprom, lcd driver, or d/a converter. it provides either master or slave mode, high - speed rate up to f sys / 2 , transfer complete and write collision flag. for a multi - master system, spi sup ports master mode fault to protect a multi - master conflict. 14.1 functional d escription figure 14 - 1 . spi block diagram figure 14 - 1 . spi block diagram shows s pi block diagram. it provides an overview of spi architecture in this device. the main blocks of spi are the spi control register logic, spi status logic, clock rate control logic, and pin control logic. for a serial data transfer or receiving, the spi blo ck exists a write d i v i d e r / 2 , / 4 , / 8 , / 1 6 s e l e c t m s b l s b p i n c o n t o r l l o g i c m i s o m o s i s p c l k s s s p i s t a t u s c o n t r o l l o g i c s p i s t a t u s r e g i s t e r s p i c o n t r o l r e g i s t e r c l o c k l o g i c s m m s c l o c k s p i f w c o l s p i o v f m o d f d i s m o d f s p i i n t e r r u p t s p i e n m s t r m s t r s s o e d i s m o d f s p r 0 s p r 1 s p r 0 s p r 1 c p h a c p o l m s t r l s b f e s p i e n s s o e s p i e n i n t e r n a l d a t a b u s f s y s w r i t e d a t a b u f f e r 8 - b i t s h i f t r e g i s t e r r e a d d a t a b u f f e r
N76E003 datasheet jun 26 , 201 7 page 137 of 267 rev. 1.02 data buffer, a shift out register and a read data buffer. it is double buffered in the receiving and transmit direction s . transmit data can be written to the shifter until when the previous transfer is not complete. receiving logic consis ts of parallel read data buffer so the shift register is free to accept a second data, as the first received data will be transferred to the read data buffer. the four pins of spi interface are master - in/slave - out (miso), master - out/slave - in (mosi), shift clock (spclk), and slave select ( ? ? ? ? ). the mosi pin is used to transfer a 8 - bit data in series from the master to the slave. therefore, mosi is an output pin for master device and a n input for slave. respectively, the miso is used to receive a serial data from the slave to the master. the spclk pin is the clock output in master mode, but is the clock input in slave mode. the shift clock is used to synchronize the data movement both in and out of the devices through their mosi and miso pins. the shift clock is driven by the master mode device for eight clock cycles . eight clocks exchange one byte data on the serial lines. for the shift clock is always produced out of the master device, the system should never exist more than one device in master mode for avo iding device conflict. each slave peripheral is selected by one slave select pin ( ? ? ? ? ). the signal should stay low for any slave access. when ? ? ? ? is driven high, the slave device will be inactivated. if the system is multi - slave, there should be only one slave device selected at the same time. in the master mode mcu, the ? ? ? ? pin does not function and it can be configured as a general purpose i/o. however, ? ? ? ? can be used as master mode fault detection (see section 14.5 mode fault detection on page 146 ) via software setting if multi - master environment exists. the N76E003 also provides auto - activating function to toggle ? ? ? ? between each b yte - transfer. m i s o m o s i s p c l k s s i / o p o r t 0 1 2 3 i / o p o r t 0 1 2 3 s o s i s c k s s s l a v e d e v i c e 1 m a s t e r / s l a v e m c u 1 m i s o m o s i s p c l k s s m a s t e r / s l a v e m c u 2 s o s i s c k s s s l a v e d e v i c e 2 s o s i s c k s s s l a v e d e v i c e 3
N76E003 datasheet jun 26 , 201 7 page 138 of 267 rev. 1.02 figure 14 - 2 . spi multi - m aster, multi - s lave interconnection figure 14 - 2 shows a typical interconnection of spi devices. the bus generally connects devices together through three signal wires, mosi to mosi, miso to miso, and spclk to spclk. the master devices select the individual slave devices by using four pins of a parallel port to control the four ? ? ? ? pins. mcu1 and mcu2 pl ay either master or slave mode. the ? ? ? ? should be configured as master mode fault detection to avoid multi - master conflict. figure 14 - 3 . spi single - m aster, single - s lave intercon nection figure 14 - 3 shows the simplest spi system interconnection, single - master and signal - slave. during a transfer, the master shifts data out to the slave via mosi line. while simultaneously, the master shifts data in from the slave via miso line. the two shift registers in the master mcu and the slave mcu can be considered as one 16 - bit circular shift register. therefore, while a transfer data pushed from master into slave, the data in slave will also be pulled in master device respectively. the transfer effectively exchanges the data , which was in the spi shift registers of the two mcus. by default, spi data is transferred msb first. if the lsbfe (spcr.5) is set, spi data shifts lsb first. this bit does not af fect the position of the msb and lsb in the data register. note that all the following description and figures are under the condition of lsbfe logic 0. msb is transmitted and received first. there are three spi registers to support its operations, includi ng spi control register (spcr), spi status register (spsr), and spi data register (spdr). these registers provide control, status, data storage functions, and clock rate selection. the following registers relate to spi function. s p i c l o c k g e n e r a t o r m i s o m i s o m o s i m o s i s p c l k s p c l k g n d s s s s 7 6 5 4 3 2 1 0 s p i s h i f t r e g i s t e r 7 6 5 4 3 2 1 0 s p i s h i f t r e g i s t e r m a s t e r m c u s l a v e m c u * * s s c o n f i g u r a t i o n f o l l o w s d i s m o d f a n d s s o e b i t s .
N76E003 datasheet jun 26 , 201 7 page 139 of 267 rev. 1.02 spcr C serial peripheral co ntrol register 7 6 5 4 3 2 1 0 ssoe spien lsbfe mstr cpol cpha spr1 spr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f3h , page 0 reset value : 0000 0000b bit name description 7 ssoe slave select output enable this bit is used in combination with the dismod f (spsr.3) bit to determine the feature of ? ? ? ? pin as shown in table 14 - 1 . slave select pin configurations . this bit takes effect only under mstr = 1 and dismodf = 1 condition. 0 = ? ? ? ? functions as a general purp ose i/o pin. 1 = ? ? ? ? automatically goes low for each transmission when selecting external slave device and goes high during each idle state to de - select the slave device. 6 spien spi enable 0 = spi function disable d . 1 = spi function enable d . 5 lsbfe ls b first enable 0 = the spi data is transferred msb first. 1 = the spi data is transferred lsb first. 4 mstr master mode enable this bit switches the spi operating between master and slave modes. 0 = the spi is configured as slave mode. 1 = the spi is conf igured as master mode. 3 cpol spi clock polarity select cpol bit determines the idle state level of the spi clock. see figure 14 - 4 . spi clock formats . 0 = the spi clock is low in idle state. 1 = the spi clock is h igh in idle state. 2 cpha spi clock phase select cpha bit determines the data sampling edge of the spi clock. see figure 14 - 4 . spi clock formats . 0 = the data is sampled on the first edge of the spi clock. 1 = the data is sampled on the second edge of the spi clock.
N76E003 datasheet jun 26 , 201 7 page 140 of 267 rev. 1.02 bit name description 1:0 spr[1:0] spi clock rate select these two bits select four grades of spi clock divider. the clock rates below are illustrated under f sys = 16 mhz condition. spr1 spr0 divider spi clock rate 0 0 2 8 m bit/s 0 1 4 4 m bit/s 1 0 8 2 m bit/s 1 1 16 1 m bit/s spr[1:0] are valid only under master mode (mstr = 1). if under slave mode, the clock will automatically synchronize with the external clock on spiclk pin from mas ter device up to f sys / 2 communication speed. sp cr 2 C serial peripheral control register 2 7 6 5 4 3 2 1 0 - - - - - - spis1 sp is0 - - - - - - r/w r/w address: f3h , page 1 reset value: 0000 0000b bit name description 7:2 - reserved 1:0 sp is [1:0] spi i nterval time select ion between adjacent bytes spis[1:0] and cpha select eight grades of spi interval time selection between adjacent bytes . as below table: cpha spis 1 spis 0 spi clock 0 0 0 0.5 0 0 1 1 .0 0 1 0 1.5 0 1 1 2 .0 1 0 0 1 .0 1 0 1 1.5 1 1 0 2 .0 1 1 1 2.5 spis [1:0] are valid only under master mode (ms tr = 1).
N76E003 datasheet jun 26 , 201 7 page 141 of 267 rev. 1.02 table 14 - 1 . slave select pin configurations dismodf ssoe master mode (mstr = 1) slave mode (mstr = 0) 0 x ? ? ? ? input for mode fault ? ? ? ? input for slave select 1 0 general purpose i/o 1 1 automatic ? ? ? ? output spsr C serial peripheral status register 7 6 5 4 3 2 1 0 spif wcol spiovf modf dismodf - - - r/w r/w r/w r/w r/w - - - address: f4h reset value : 0000 0000b bit name descri ption 7 spif spi complete flag this bit is set to logic 1 via hardware while an spi data transfer is complete or an receiving data has been moved into the spi read buffer. if espi (eie .0) and ea are enabled, an spi interrupt will be required. this bit sh ould be cleared via software. attempting to write to spdr is inhibited if spif is set. 6 wcol write collision error flag this bit indicates a write collision event. once a write collision event occurs, this bit will be set. it should be cleared via softwa re. 5 spiovf spi overrun error flag this bit indicates an overrun event. once an overrun event occurs, this bit will be set. if espi and ea are enabled, an spi interrupt will be required. this bit should be cleared via software. 4 modf mode fault error f lag this bit indicates a mode fault error event. if ? ? ? ? pin is configured as mode fault input (mstr = 1 and dismodf = 0) and ? ? ? ? is pulled low by external devices, a mode fault error occurs. instantly modf will be set as logic 1. if espi and ea are enabl ed, an spi interrupt will be required. this bit should be cleared via software. 3 dismodf dis able mode fault error detection this bit is used in combination with the ssoe (spcr.7) bit to determine the feature of ? ? ? ? pin as shown in table 14 - 1 . slave select pin configurations . dismodf is valid only in master mode (mstr = 1). 0 = mode fault detection en abled. ? ? ? ? serves as input pin for mode fault detection disregard of ssoe. 1 = mode fault detection d isabled. the feature of ? ? ? ? follows ssoe bit.
N76E003 datasheet jun 26 , 201 7 page 142 of 267 rev. 1.02 spdr C serial peripheral data register 7 6 5 4 3 2 1 0 spdr[7:0] r/w address: f5h reset value : 0000 0000b bit name description 7:0 spdr[7:0] serial peripheral data this byte is used for transmitting or receiving data on spi bus. a write of this byte is a write to the shift register. a read of this byte is actually a read of the read data buffer. in master mode, a write to this register initiates transmission and reception of a byte simultaneously. 14.2 operating modes mast er m ode 14.2.1 the spi can operate in master mode while mstr (spcr.4) is set as 1. only one master spi device can initiate transmissions. a transmission always begins by master through writing to spdr. the byte written to spdr begins shifting out on mosi pin unde r the control of spclk. simultaneously, another byte shifts in from the slave on the miso pin. after 8 - bit data transfer complete, spif (spsr.7) will automatically set via hardware to indicate one byte data transfer complete. at the same time, the data rec eived from the slave is also transferred in spdr. user can clear spif and read data out of spdr. slave mode 14.2.2 when mstr is 0, the spi operates in slave mode. the spclk pin becomes input and it will be clocked by another master spi device. the ? ? ? ? ? pin also becomes input. the master device cannot exchange data with the slave device until the ? ? ? ? ? pin of the slave device is externally pulled low. before data transmissions occurs, the ? ? ? ? ? of the slave device should be pulled and remain low until the transmissi on is complete. if ? ? ? ? ? goes high, the spi is forced into idle state. if the ? ? ? ? ? is force d to high at the middle of transmission, the transmission will be aborted and the rest bits of the receiving shifter buffer will be high and goes into idle state. in slave mode, data flows from the master to the slave on mosi pin and flows from the slave to the master on miso pin. the data enters the shift register under the control of the spclk from the master device. after one byte is received in the shift register, it is immediately moved into the read data buffer and the spif bit is set. a read of the spdr is actually a read of the read data buffer. to prevent an overrun and the loss of the byte that caused by the overrun, the slave should read spdr out and the firs t spif should be cleared before a second transfer of data from the master device comes in the read data buffer.
N76E003 datasheet jun 26 , 201 7 page 143 of 267 rev. 1.02 14.3 clock formats and data transfer to accommodate a wide variety of synchronous serial peripherals, the spi has a clock polarity bit cpol (spcr.3) and a clock phase bit cpha (spcr.2). figure 14 - 4 . spi clock formats shows that cpol and cpha compose four different clock formats. the cpol bit denotes the spclk line level in its idle state. the cpha bit defines t he edge on which the mosi and miso lines are sampled. the cpol and cpha should be identical for the master and slave devices on the same system. to communicate in different data formats with one another will result undetermined result. figure 14 - 4 . spi clock formats in spi, a master device always initiates the transfer. if spi is selected as master mode (mstr = 1) and enabled (spien = 1), writing to the spi data register (spdr) by the master device starts the spi clock and data transfer. after shifting one byte out and receiving one byte in, the spi clock stops and spif (spsr.7) is set in both master and slave. if spi interrupt enable bit espi (eie.0) is set 1 and global interrupt is enabled (ea = 1), the interrupt service routine (isr) of spi will be executed. concerning the slave mode, the ? ? ? ? ? signal needs to be taken care. as shown in figure 14 - 4 . spi clock formats , when cpha = 0, the fi rst spclk edge is the sampling strobe of msb (for an example of lsbfe = 0, msb first). therefore, the slave should shift its msb data before the first spclk edge. the falling edge of ? ? ? ? ? is used for preparing the msb on miso line. the ? ? ? ? ? pin therefore s hould toggle high and then low between each successive serial byte. furthermore, if the slave writes data to the spi data register (spdr) while ? ? ? ? ? is low, a write collision error occurs. when cpha = 1, the sampling edge thus locates on the second edge of spclk clock. the slave uses the first spclk clock to shift msb out rather than the ? ? ? ? ? falling edge. therefore, the ? ? ? ? ? line can remain low between successive transfers. this format may be preferred in systems having single fixed c p h a = 0 c p h a = 1 s a m p l e c p o l = 0 c p o l = 1 c l o c k p h a s e ( c p h a ) c l o c k p o l a r i t y ( c p o h ) s a m p l e s a m p l e s a m p l e
N76E003 datasheet jun 26 , 201 7 page 144 of 267 rev. 1.02 master and single fixed slave. the ? ? ? ? ? line of the unique slave device can be tied to gnd as long as only cpha = 1 clock mode is used. the spi should be configured before it is enabled (spien = 1) , or a change of lsbfe, mstr, cpol, cpha and spr[1:0] will abort a transmission in progress and force the spi system into idle state. prior to any configuration bit changed, spien must be disabled first. figure 14 - 5 . spi clock and data format with cpha = 0 s p c l k c y c l e s s p c l k ( c p o l = 0 ) m o s i s s o u t p u t o f m a s t e r [ 2 ] s p i f ( m a s t e r ) 1 2 3 4 5 6 7 8 s p c l k ( c p o l = 1 ) t r a n s f e r p r o g r e s s [ 1 ] ( i n t e r n a l s i g n a l ) m s b m i s o 6 5 4 3 2 1 l s b m s b i n p u t t o s l a v e s s l s b 6 5 4 3 2 1 s p i f ( s l a v e ) [ 1 ] t r a n s f e r p r o g r e s s s t a r t s b y a w r i t i n g s p d r o f m a s t e r m c u . [ 2 ] s s a u t o m a t i c o u t p u t a f f e c t s w h e n m s t r = d i s m o d f = s s o e = 1 . s p c l k c y c l e s
N76E003 datasheet jun 26 , 201 7 page 145 of 267 rev. 1.02 figure 14 - 6 . spi clock and data format with cpha = 1 14.4 slave select pin configuration the N76E003 spi gives a flexible ? ? ? ? ? pin feature for different system requirements. when the spi o perates as a slave, ? ? ? ? ? pin always rules as slave select input. when the master mode is enabled, ? ? ? ? ? has three different functions according to dismodf (spsr.3) and ssoe (spcr.7). by default, dismodf is 0. it means that the mode fault detection activates . ? ? ? ? ? is configured as a input pin to check if the mode fault appears. on the contrary, if dismodf is 1, mode fault is inactivated and the ssoe bit takes over to control the function of the ? ? ? ? ? pin. while ssoe is 1, it means the slave select signal will generate automatically to select a slave device. the ? ? ? ? ? as output pin of the master usually connects with the ? ? ? ? ? input pin of the slave device. the ? ? ? ? ? output automatically goes low for each transmission when selecting external slave device and goes h igh during each idle state to de - select the slave device. while ssoe is 0 and dismodf is 1, ? ? ? ? ? is no more used by the spi and reverts to be a general purpose i/o pin. t r a n s f e r p r o g r e s s [ 1 ] ( i n t e r n a l s i g n a l ) s p c l k c y c l e s s p c l k ( c p o l = 0 ) m o s i s s o u t p u t o f m a s t e r [ 2 ] s p i f ( m a s t e r ) 1 2 3 4 5 6 7 8 s p c l k ( c p o l = 1 ) m s b m i s o 6 5 4 3 2 1 l s b m s b i n p u t t o s l a v e s s l s b 6 5 4 3 2 1 s p i f ( s l a v e ) [ 1 ] t r a n s f e r p r o g r e s s s t a r t s b y a w r i t i n g s p d r o f m a s t e r m c u . [ 2 ] s s a u t o m a t i c o u t p u t a f f e c t s w h e n d i s m o d f = s s o e = m s t r = 1 . [ 3 ] i f s s o f s l a v e i s l o w , t h e m i s o w i l l b e t h e l s b o f p r e v i o u s d a t a . o t h e r w i s e , m i s o w i l l b e h i g h . [ 4 ] w h i l e s s s t a y s l o w , t h e l s b w i l l l a s t i t s s t a t e . o n c e s s i s r e l e a s e d t o h i g h , m i s o w i l l s w i t c h t o h i g h l e v e l . [ 3 ] [ 4 ] s p c l k c y c l e s
N76E003 datasheet jun 26 , 201 7 page 146 of 267 rev. 1.02 14.5 mode fault detection the mode fault detection is useful in a system where more than one spi devices might become masters at the same time. it may induce data contention. when the spi device is configured as a master and the ? ? ? ? ? input line is configured for mode fault input depending on table 14 - 1 . slave select pin configurations , a mode fault error occurs once the ? ? ? ? ? is pulled low by others. it indicates that some other spi device is trying to address this master as if it is a slave. instantly the mstr and spien control bits in the spcr are cleared via hardware to disable spi, mode fault flag modf (spsr.4) is set and an interrupt is generated if espi ( eie .0) and ea are enabled. 14.6 write collision error the spi is signal buffered in the transfer direction and double buffered in the receiving and transm it direction . new data for transmission cannot be written to the shift register until the previous transaction is complete. write collision occurs while spdr be writ t e n more than once while a transfer was in progress. spdr is double buffered in the transmi t direction. any writing to spdr cause data to be written directly into the spi shift register. once a write collision error is generated, wcol (spsr.6) will be set as 1 via hardware to indicate a write collision. in this case, the current transferring dat a continues its transmission. however the new data that caused the collision will be lost. although the spi logic can detect write collisions in both master and slave modes, a write collision is normally a slave error because a slave has no indicator when a master initiates a transfer. during the receiving of slave, a write to spdr causes a write collision in slave mode. wcol flag needs to be cleared via software. 14.7 overrun error for receiving data, the spi is double buffered in the receiving direction. the r eceived data is transferred into a parallel read data buffer so the shifter is free to accept a second serial byte. however, the received data should be read from spdr before the next data has been completely shifted in. as long as the first byte is read o ut of the read data buffer and spif is cleared before the next byte is ready to be transferred, no overrun error condition occurs. otherwise the overrun error occurs. in this condition, the second byte data will not be successfully received into the read d ata register and the previous data will remains. if overrun occur, spiovf (spsr.5) will be set via hardware. an spiovf setting will also require an interrupt if enabled. figure 14 - 7 . spi overrun waveform shows the relationship between the data receiving and the overrun error.
N76E003 datasheet jun 26 , 201 7 page 147 of 267 rev. 1.02 figure 14 - 7 . spi overrun waveform 14.8 spi interrupt three spi status flags, spif, modf, and spiovf, can generate an spi event interrupt requests. all of them locate in spsr. spif will be set after completion of data transfer with external device or a new data have been received and copied to spdr. modf becomes set to indicate a low level on ? ? ? ? ? causing the mode fault stat e. spiovf denotes a receiving overrun error. if spi interrupt mask is enabled via setting espi (eie. 6 ) and ea is 1, cpu will executes the spi interrupt service routine once any of these three flags is set. user needs to check flags to determine what event caused the interrupt. these three flags are software cleared. figure 14 - 8 . spi interrupt request s h i f t i n g d a t a [ n ] i n s h i f t i n g d a t a [ n + 1 ] i n s p i f d a t a [ n ] d a t a [ n ] r e a d d a t a b u f f e r s h i f t r e g i s t e r s h i f t i n g d a t a [ n + 2 ] i n s p i o v f d a t a [ n + 2 ] d a t a [ n ] r e c e i v i n g b e g i n s d a t a [ n + 1 ] r e c e i v i n g b e g i n s d a t a [ n + 2 ] r e c e i v e i n g b e g i n s [ 1 ] w h e n d a t a [ n ] i s r e c e i v e d , t h e s p i f w i l l b e s e t . [ 2 ] i f s p i f i s n o t c l e a r b e f o r e d a t a [ n + 1 ] p r o g r e s s d o n e , t h e s p i o v f w i l l b e s e t . d a t a [ n ] w i l l b e k e p t i n r e a d d a t a b u f f e r b u t d a t a [ n + 1 ] w i l l b e l o s t . [ 3 ] s p i f a n d s p i o v f m u s t b e c l e a r e d b y s o f t w a r e . [ 4 ] w h e n d a t a [ n + 2 ] i s r e c e i v e d , t h e s p i f w i l l b e s e t a g a i n . [ 1 ] [ 2 ] [ 3 ] [ 3 ] [ 4 ] s p i f d i s m o d f m s t r e s p i ( e i e . 6 ) s p i i n t e r r u p t s p i o v f m o d e f a u l t d e t e c t i o n s s m o d f e a
N76E003 datasheet jun 26 , 201 7 page 148 of 267 rev. 1.02 15. inter - integrated circuit ( i 2 c) the inter - integrated circuit (i 2 c) bus serves as a n serial interface between the microcontroller s and the i 2 c devices such as eeprom, lcd module, temperature sensor, and so on. the i 2 c bus used two wires design (a serial data line sda and a serial clock line scl) to transfer information between devices. t he i 2 c bus uses bi - directional data transfer between masters and slaves. there is no central master and the multi - master system is allowed by arbitration between simultaneously transmitting masters. the serial clock synchronization allows devices with diff erent bit rates to communicate via one serial bus. the i 2 c bus supports four transfer modes including master transmitter, master receiver, slave receiver, and slave transmitter. the i 2 c interface only supports 7 - bit addressing mode. a special mode general call is also available. the i 2 c can meet both standard (up to 100kbps) and fast (up to 400k bps) speeds. 15.1 functional d escription for a bi - directional transfer operation, the sda and scl pins should be open - drain pads. this implements a wired - and function , w hich is essential to the operation of the interface. a low level on a i 2 c bus line is generated when one or more i 2 c devices output a . a high level is generated when all i 2 c devices output , allowing the pull - up resistors to pull the line high. in n 76e003 , user should set output latches of scl and sda . a s logic 1 before enabling the i 2 c funct ion by setting i2cen (i2con.6). figure 15 - 1 . i 2 c b us interconnection the i 2 c is con sidered free when both lines are high. meanwhile, any device , which can operate as a master can occupy the bus and generate one transfer after generating a start condition. the bus now is considered busy before the transfer ends by sending a stop condition . the master generates s d a s c l s l a v e d e v i c e s d a s c l o t h e r m c u s d a s c l v d d r u p r u p s d a s c l n 7 6 e 0 0 3
N76E003 datasheet jun 26 , 201 7 page 149 of 267 rev. 1.02 all of the serial clock pulses and the start and stop condition. however if there is no start condition on the bus, all devices serve as not addressed slave. the hardware looks for its own slave address or a general call address. (th e general call address detection may be enabled or disabled by gc (i2addr.0).) if the matched address is received, an interrupt is requested. every transaction on the i 2 c bus is 9 bits long, consisting of 8 data bits (msb first) and a single acknowledge b it. the number of bytes per transfer (defined as the time between a valid start and stop condition) is unrestricted but each byte has to be followed by an acknowledge bit. the master device generates 8 clock pulse to send the 8 - bit data. after the 8 th fall ing edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the 9 th clock pulse. after 9 th clock pulse, the data receiving device can hold scl line stretched low if next receiving is not prepared ready. it forces the next byte transaction suspended. the data transaction continues when the receiver releases the scl line. figure 15 - 2 . i 2 c bus protocol start and st op condition 15.1.1 the protocol of the i 2 c bus defines two states to begin and end a transfer, start (s) and stop (p) conditions. a start condition is defined as a high - to - low transition on the sda line while scl line is high. the stop condition is defined as a low - to - high transition on the sda line while scl line is high. a start or a stop condition is always generated by the master and i 2 c bus is considered busy after a start condition and free after a stop condition. after issuing the stop condition successful , the original master device will release the control authority and turn back as a not addressed slave. consequently, the original addressed slave will become a not addressed slave. the i 2 c bus is free and listens to next start condition of next transfer. a data transfer is always terminated by a stop condition generated by the master. however, if a master still wishes to communicate on the bus, it can generate a repeated start (sr) condition and address the pervious or another slave without first generatin g a stop condition. various combinations of read/write formats are then possible within such a transfer. s d a s c l m s b l s b a c k 1 2 8 9 s t a r t c o n d i t i o n s t o p c o n d i t i o n
N76E003 datasheet jun 26 , 201 7 page 150 of 267 rev. 1.02 figure 15 - 3 . start, repeated start, and stop conditions 7 - b it address wit h data format 15.1.2 following the start condition is generated, one byte of special data should be transmitted by the master. it includes a 7 - bit long slave address (sla) following by an 8 th bit, which is a data direction bit (r/w), to address the target slave d evice and determine the direction of data flow. if r/w bit is 0, it indicates that the master will write information to a selected slave. also, if r/w bit is 1, it indicates that the master will read information from the addressed slave. an address packet consisting of a slave address and a read i or a write (w) bit is called sla+r or sla+w, respectively. a transmission basically consists of a start condition, a sla+w/r, one or more data packets and a stop condition. after the specified slave is addressed b y sla+w/r, the second and following 8 - bit data bytes issue by the master or the slave devices according to the r/w bit configuration. here is an exception called general all address , which can address all devices by giving the first byte of data all 0. a general call is used when a master wishes to transmit the same message to several slaves in the system. when this address is used, other devices may respond with an acknowledge or ignore it according to individual software configuration. if a device res ponse the general call, it operates as like in the slave - receiver mode. note that the address 0x00 is reserved for general call and cannot be used as a slave address, therefore, in theory, a 7 - bit addressing i 2 c bus accepts 127 devices with their slave add resses 1 to 127. figure 15 - 4 . data format of one i 2 c transfer s d a s c l s t a r t s t o p s t a r t r e p e a t e d s t a r t s t o p s d a s c l 1 - 7 8 9 8 9 1 - 7 1 - 7 8 9 a d d r e s s w / r a c k s p d a t a a c k d a t a a c k
N76E003 datasheet jun 26 , 201 7 page 151 of 267 rev. 1.02 during the data transaction period, the data on the sda line should be stable during the high period of the clock, a nd the data line can only change when scl is low. acknowledge 15.1.3 th e 9 th scl pulse for any transferred byte is dedicated as an acknowledge (ack). it allows receiving devices (which can be the master or slave) to respond back to the transmitter (which also can be the master or slave) by pulling the sda line low. the acknowledge - related clock pulse is generated by the master. the transmitter should release control of sda line during the acknowledge clock pulse. the ack is an active - low signal, pulling the sda li ne low during the clock pulse high duty, indicates to the transmitter that the device has received the transmitted data. commonly, a receiver , which has been addressed is requested to generate an ack after each byte has been received. when a slave receiver does not acknowledge (nack) the slave address, the sda line should be left high by the slave so that the mater can generate a stop or a repeated start condition. if a slave - receiver does acknowledge the slave address, it switches itself to not addressed s lave mode and cannot receive any more data bytes. this slave leaves the sda line high. the master should generate a stop or a repeated start condition. if a master - receiver is involved in a transfer, because the master controls the number of bytes in the t ransfer, it should signal the end of data to the slave - transmitter by not generating an acknowledge on the last byte. the slave - transmitter then switches to not addressed mode and release s the sda line to allow the master to generate a stop or a repeated s tart condition. figure 15 - 5 . acknowledge bit arbitration 15.1.4 a master may start a transfer only if the bus is free. it is possible for two or more masters to generate a start conditi on. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the competing master devices to place a 1 (high) on sda while s d a o u t p u t b y t r a n s m i t t e r s c l f r o m m a s t e r 1 2 8 9 s t a r t c o n d i t i o n s d a o u t p u t b y r e c e i v e r s d a = 0 , a c k n o w l e d g e ( a c k ) s d a = 1 , n o t a c k n o w l e d g e ( n a c k ) c l o c k p u l s e f o r a c k n o w l e d g e b i t
N76E003 datasheet jun 26 , 201 7 page 152 of 267 rev. 1.02 another master transmits a 0 (low) switches off its data outpu t stage because the level on the bus does not match its own level. the arbitration lost master switches to the not addressed slave immediately to detect its own slave address in the same serial transfer whether it is being addressed by the winning master. it also releases sda line to high level for not affecting the data transfer continued by the winning master. however, the arbitration lost master continues generating clock pulses on scl line until the end of the byte in which it loses the arbitration. arb itration is carried out by all masters continuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value that the master has to output, it has lost the arbitration. note that a master can only lose arb itration when it outputs a high sda value while another master outputs a low value. arbitration will continue until only one master remains, and this may take many bits. its first stage is a comparison of address bits, and if both masters are trying to add ress the same device, arbitration continues on to the comparison of data bits or acknowledge bit. figure 15 - 6 . arbitration procedure of two masters since control of the i 2 c bus i s decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus. slaves are not involved in the arbitration procedure. 15.2 control registers of i 2 c there are five control regis ters to interface the i 2 c bus including i2con, i2stat, i2dat, i2addr, and i2clk. these registers provide protocol control, status, data transmitting and receiving functions, and clock rate configuration. for application flexibility, sda and scl pins can be exchanged by i2c px ( i2con . 0 ). the following registers relate to i 2 c function. d a t a 1 f r o m m a s t e r 1 s t a r t c o n d i t i o n m a s t e r 1 l o s e s a r b i t r a t i o n f o r d a t a 1 s d a i t i m m e d i a t e l y s w i t c h e s t o n o t a d d r e s s e d s l a v e a n d o u t p u t s h i g h l e v e l d a t a 2 f r o m m a s t e r 2 s d a l i n e s c l l i n e
N76E003 datasheet jun 26 , 201 7 page 153 of 267 rev. 1.02 i2con C i 2 c control ( bit - addressable ) 7 6 5 4 3 2 1 0 - i2cen sta sto si aa - i2c px - r/w r/w r/w r/w r/w - r/w address: c0 h reset value : 0000 0000b bit name description 7 - reserved 6 i2cen i 2 c bus enable 0 = i 2 c bus d isabled. 1 = i 2 c bus e nabled. before enabling the i 2 c, scl and sda port latches should be set to logic 1. 5 sta start flag when sta is set, the i 2 c generates a start condition if the bus is free. if the bus i s busy, the i 2 c waits for a stop condition and generates a start condition following. if sta is set while the i 2 c is already in the master mode and one or more bytes have been transmitted or received, the i 2 c generates a repeated start condition. note that sta can be set anytime even in a slave mode, but sta is not hardware automatically cleared after start or repeated start condition has been detected. user should take care of it by clearing sta manually. 4 sto stop flag when sto is set if the i 2 c is in t he master mode, a stop condition is transmitted to the bus. sto is automatically cleared by hardware once the stop condition has been detected on the bus. the sto flag setting is also used to recover the i 2 c device from the bus error state (i2stat as 00h). in this case, no stop condition is transmitted to the i 2 c bus. if the sta and sto bits are both set and the device is original in the master mode, the i 2 c bus will generate a stop condition and immediately follow a start condition. if the device is in sla ve mode, sta and sto simultaneous setting should be avoid from issuing illegal i 2 c frames. 3 si i 2 c interrupt flag si flag is set by hardware when one of 2 6 possible i 2 c status (besides f8h status) is entered. after si is set, the software should read i2s tat register to determine which step has been passed and take actions for next step. si is cleared by software. before the si is cleared, the low period of scl line is stretched. the transaction is suspended. it is useful for the slave device to deal with previous data bytes until ready for receiving the next byte. the serial transaction is suspended until si is cleared by software. after si is cleared, i 2 c bus will continue to generate start or repeated start condition, stop condition, 8 - bit data, or so on depending on the software configuration of controlling byte or bits. therefore , user should take care of it by preparing suitable setting of registers before si is software cleared.
N76E003 datasheet jun 26 , 201 7 page 154 of 267 rev. 1.02 bit name description 2 aa acknowledge assert flag if the aa flag is set, an ack (low level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver or an own - address - matching slave. if the aa flag is cleared, a nack (high level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver or an own - address - matching slave . a device with its own aa flag cleared will ignore its own salve address and the general call. consequently, si will note be asserted and no interrupt is requested. note that if a n addressed slave does not return an ack under slave receiver mode or not receive an ack under slave transmitter mode, the slave device will become a not addressed slave. it cannot receive any data until its aa flag is set and a master addresses it again. there is a special case of i2stat value c8h occurs under slave transmitter mode. before the slave device transmit the last data byte to the master, aa flag can be cleared as 0. then after the last data byte transmitted, the slave device will actively switc h to not addressed slave mode of disconnecting with the master. the further reading by the master will be all ffh. 1 - reserved 0 i2c px i2c pin s select 0 = assign scl to p 1 . 3 and s da to p1.4. 1 = assign scl to p0. 2 and s da to p1. 6 . note that i2c pins wil l exchange immediately once setting or clearing this bit. i2stat C i 2 c status 7 6 5 4 3 2 1 0 i2stat[7:3] 0 0 0 r r r r address: bd h reset value : 1111 1000b bit name description 7 :3 i2stat[7:3] i 2 c status code the msb five bits of i2stat contains the status code. there are 2 7 possible status codes. when i2stat is f8h, no relevant state information is available and si flag keeps 0. all other 2 6 status codes correspond to the i 2 c states. when each of these status is entered, si will be set as logic 1 and a interrupt is requested. 2:0 0 reserved the least significant three bits of i2stat are always read as 0.
N76E003 datasheet jun 26 , 201 7 page 155 of 267 rev. 1.02 i2dat C i 2 c data 7 6 5 4 3 2 1 0 i2dat[7:0] r/w address: bc h reset value : 0000 0000b bit name description 7 :0 i2dat[7:0] i 2 c data i2dat contain s a byte of the i 2 c data to be transmitted or a byte , which has just received. data in i2dat remains as long as si is logic 1. the result of reading or writing i2dat during i 2 c transceiving progress is unpredicted. while data in i2dat is shifted out, data on the bus is simultaneously being shifted in to update i2dat. i2dat always shows the last byte that presented on the i 2 c bus. thus the event of lost arbitration, the original value of i2dat changes after the transaction. i2addr C i 2 c own slave address 7 6 5 4 3 2 1 0 i2addr[7:1] gc r/w r/w address: c1 h reset value : 0000 0000b bit name description 7:1 i2addr[7:1] i 2 c devices own slave address in master mode: these bits have no effect. in slave mode: these 7 bits define the slave address of this i 2 c de vice by user. the master should address i 2 c device by sending the same address in the first byte data after a start or a repeated start condition. if the aa flag is set, this i 2 c device will acknowledge the master after receiving its own address and become an addressed slave. otherwise, the addressing from the master will be ignored. note that i2addr[7:1] should not remain its default value of all 0, because address 0x00 is reserved for general call. 6 gc general call bit in master mode: this bit has no ef fect. in slave mode: 0 = the general call is always ignored. 1 = the general call is recognized if aa flag is 1; otherwise, it is ignored if aa is 0.
N76E003 datasheet jun 26 , 201 7 page 156 of 267 rev. 1.02 i2clk C i 2 c clock 7 6 5 4 3 2 1 0 i2clk[7:0] r/w address: be h reset value : 0000 10 01 b bit name descrip tion 7:0 i2clk[7:0] i 2 c clock setting in master mode: this register determines the clock rate of i 2 c bus when the device is in a master mode. the clock rate follows the equation, . the default value will make the clock rate of i 2 c bu s 400k bps if the peripheral clock is 16 mhz . note that the i2clk value of 00h and 01h are not valid. this is an implement limitation. in slave mode: this byte has no effect. in slave mode, the i 2 c device will automatically synchronize with any given clock rate up to 400k b ps. 15.3 operating modes in i 2 c protocol definition, there are four operating modes including master transmitter, master receiver, slave receiver, and slave transmitter. there is also a special mode called general call. its operating is simil ar to master transmitter mode. master transmitter mode 15.3.1 in the master transmitter mode, several bytes of data are transmitted to a slave receiver. the master should prepare by setting desired clock rate in i2clk. the master transmitter mode may now be enter ed by setting sta (i2con.5) bit as 1. the hardware will test the bus and generate a start condition as soon as the bus becomes free. after a start condition is successfully produced, the si flag (i2con.3) will be set and the status code in i2stat show 08h. the progress is continued by loading da with the target slave address and the data direction bit write ( a+w). he bit should then be cleared to commence sla+w transaction. after the sla+w byte has been transmitted and an acknowledge (ack) has be en returned by the addressed slave device, the si flag is set again and i2stat is read as 18h. the appropriate action to be taken follows user defined communication protocol by sending data continuously. after all data is transmitted, the master can send a stop condition by setting sto (i2con.4) and then clearing si to terminate the transmission. a repeated start condition can also be generated without sending stop condition to immediately initial another transmission. ) 1 + clk 2 i ( 4 f sys
N76E003 datasheet jun 26 , 201 7 page 157 of 267 rev. 1.02 figure 15 - 7 . flow and status of master transmitter mode master receiver mode 15.3.2 in the master receiver mode, several bytes of data are received from a slave transmitter. the transaction is initialized just as the master transmitter mode. following the start condition, i2dat should be loaded with the target slave address and the data direction bit read ( a+ ). after the sla+r byte is transmitted and an acknowledge bit has been returned, the si flag is set again and i2s tat is read as 40h. si flag then should be cleared to receive data from the slave transmitter. if aa flag (i2con.2) is set, the master receiver will acknowledge the slave transmitter. if aa is cleared, the 0 8 h a s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) i 2 d a t = s l a + w s l a + w w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d 1 8 h s l a + w h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d o r 2 0 h s l a + w h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a r e p e a t e d s t a r t w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) i 2 d a t = d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 1 , 0 , x ) a s t o p w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 1 , 0 , x ) a s t o p f o l l o w e d b y a s t a r t w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d 2 8 h d a t a b y t e h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d o r 3 0 h d a t a b y t e h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d 1 0 h a r e p e a t e d s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) i 2 d a t = s l a + r s l a + r w i l l b e t r a n s m i t t e d 3 8 h a r b i t r a t i o n l o s t i n s l a + w o r d a t a b y t e t o m a s t e r r e c e i v e r 6 8 h o r 7 8 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e r e c e i v e r a c k h a s b e e n t r a n s m i t t e d o r b 0 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e t r a n s m i t t e r a c k h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) i 2 d a t = s l a + w s l a + w w i l l b e t r a n s m i t t e d m r m t t o c o r r e s p o n d i n g s l a v e m o d e n o r m a l a r b i t r a t i o n l o s t
N76E003 datasheet jun 26 , 201 7 page 158 of 267 rev. 1.02 master receiver will not acknowledge the slave and release the slave transmitter as a not addressed slave. after that, the master can generate a stop condition or a repeated start condition to terminate the transmission or initial another one. figure 15 - 8 . flow and status of master receiver mode slave receiver mode 15.3.3 in the slave receiver mode, several bytes of data are received form a master transmitter. before a transmission is commenced, i2addr should be loaded with the address to which the device will respond when addressed by a master. i2clk does not affect in slave mode. the aa bit should be set 0 8 h a s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) i 2 d a t = s l a + r s l a + r w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d 4 0 h s l a + r h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d o r 4 8 h s l a + r h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a r e p e a t e d s t a r t w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) d a t a b y t e w i l l b e r e c e i v e d a c k w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 1 , 0 , x ) a s t o p w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 1 , 0 , x ) a s t o p f o l l o w e d b y a s t a r t w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d 5 0 h d a t a b y t e h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e 1 0 h a r e p e a t e d s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) i 2 d a t = s l a + w s l a + w w i l l b e t r a n s m i t t e d 3 8 h a r b i t r a t i o n l o s t i n n a c k b i t t o m a s t e r t r a n s m i t t e r ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) d a t a b y t e w i l l b e r e c e i v e d n a c k w i l l b e t r a n s m i t t e d 5 8 h d a t a b y t e h a s b e e n r e c e i v e d n a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e 6 8 h o r 7 8 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e r e c e i v e r a c k h a s b e e n t r a n s m i t t e d o r b 0 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e t r a n s m i t t e r a c k h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) i 2 d a t = s l a + r s l a + r w i l l b e t r a n s m i t t e d m r m t t o c o r r e s p o n d i n g s l a v e m o d e n o r m a l a r b i t r a t i o n l o s t
N76E003 datasheet jun 26 , 201 7 page 159 of 267 rev. 1.02 to enable acknowledging its own slave address. after the initialization above, the i 2 c idles until it is addressed by its own address with the data direction bit write ( a+w). he slave receiver mode may also be entered if arbitration is lost. after the slave is addressed by sla+w, it should clear its si flag to receive the data from the master transmitter. if the aa bit is 0 during a transaction, the slave will return a non - acknowledge after the next received data byte. the slave will also become not addressed and isolate with the master. it cannot receive any byte of data with i2dat remaining the previous byte of data , which is just received. figure 15 - 9 . flow and status of slave receiver mode slave transmitter mode 15.3.4 in the slave transmitter mode, several bytes of data are transmitted to a master receiver. a fter i2addr and i2con values are given, the i 2 c wait until it is addressed by its own address with the data direction bit read ( a+ ). he slave transmitter mode may also be entered if arbitration is lost. after the slave is addressed by sla+r, it shoul d clear its si flag to transmit the data to the master receiver. normally the master receiver will return an acknowledge after every byte of data is transmitted by the slave. f the acknowledge is not received, it will transmit all data if it continues ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) i f o w n s l a + w i s r e c e i v e d , a c k w i l l b e t r a n s m i t t e d 6 0 h o w n s l a + w h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + w o r 6 8 h a r b i t r a t i o n l o s t a n d o w n s l a + w h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + w ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 0 ) d a t a b y t e w i l l b e r e c e i v e d n a c k w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 8 8 h d a t a b y t e h a s b e e n r e c e i v e d n a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e a 0 h a s t o p o r r e p e a t e d s t a r t h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) d a t a b y t e w i l l b e r e c e i v e d a c k w i l l b e t r a n s m i t t e d 8 0 h d a t a b y t e h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) a s t o p o r r e p e a t e d s t a r t w i l l b e r e c e i v e d
N76E003 datasheet jun 26 , 201 7 page 160 of 267 rev. 1.02 the transaction. it becomes a not addressed slave. if the aa flag is cleared during a transaction, the slave transmits the last byte of data. he next transmitting data will be all and the slave becomes not addressed. fig ure 15 - 10 . flow and status of slave transmitter mode general call 15.3.5 he general all is a special condition of slave receiver mode by been addressed with all data in slave address with data direction bit. b oth gc (i2addr.0) bit and aa bit should be set as 1 to enable acknowledging general calls. the slave addressed by a general call has different status code in i2stat with normal slave receiver mode. the general call may also be produced if arbitration is lo st. ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) i f o w n s l a + r i s r e c e i v e d , a c k w i l l b e t r a n s m i t t e d a 8 h o w n s l a + r h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + r o r b 0 h a r b i t r a t i o n l o s t a n d o w n s l a + r h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + r ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) i 2 d a t = d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d n a c k w i l l b e r e c e i v e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 c 0 h d a t a b y t e h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d a 0 h a s t o p o r r e p e a t e d s t a r t h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) i 2 d a t = d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d a c k w i l l b e r e c e i v e d b 8 h d a t a b y t e h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 0 ) i 2 d a t = l a s t d a t a b y t e l a s t d a t a b y t e w i l l b e t r a n s m i t t e d a c k w i l l b e r e c e i v e d c 8 h l a s t d a t a b y t e h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d * t h i s f l o w i s n o t r e c o m m e n d e d . i f t h e m s b o f n e x t b y t e w h i c h t h e s l a v e i s g o i n g t o t r a n s m i t i s 0 , i t w i l l h o l d s d a l i n e . t h e s t o p o r r e p e a t e d s t a r t c a n n o t b e s u c c e s s f u l l y g e n e r a t e d b y m a s t e r . * ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) a s t o p o r r e p e a t e d s t a r t w i l l b e r e c e i v e d
N76E003 datasheet jun 26 , 201 7 page 161 of 267 rev. 1.02 figure 15 - 11 . flow and status of general call mode miscellaneous states 15.3.6 there are two i2stat status codes that do not correspond to the 25 defined states, which are mentioned in previous sections. these are f8h and 00h states. the first status code f8h indicates that no relevant information is available during each transaction. meanwhile, the si flag is 0 and no i 2 c interrupt is required. the other status code 00h means a bus error has occurred during a transaction. a bus error is caused by a start or stop condition appearing temporally at an illegal position such as the second through eighth bits of an address or a data byte, and the acknowledge bit. when a bus error occurs, t he si flag is set immediately. when a bus error is detected on the i 2 c bus, the operating device immediately switches to the not addressed salve mode, releases sda and scl lines, sets the si flag, and loads i2stat as 00h. to recover from a bus error, the s to bit should be set and then si should be cleared. after that, sto is cleared by hardware and release the i 2 c bus without issuing a real stop condition waveform on i 2 c bus. ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) g c = 1 i f g e n e r a l c a l l i s r e c e i v e d , a c k w i l l b e t r a n s m i t t e d 7 0 h g e n e r a l c a l l h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = 0 0 h o r 7 8 h a r b i t r a t i o n l o s t a n d g e n e r a l c a l l h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = 0 0 h ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 0 ) d a t a b y t e w i l l b e r e c e i v e d n a c k w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 9 8 h d a t a b y t e h a s b e e n r e c e i v e d n a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e a 0 h a s t o p o r r e p e a t e d s t a r t h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) d a t a b y t e w i l l b e r e c e i v e d a c k w i l l b e t r a n s m i t t e d 9 0 h d a t a b y t e h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) a s t o p o r r e p e a t e d s t a r t w i l l b e r e c e i v e d
N76E003 datasheet jun 26 , 201 7 page 162 of 267 rev. 1.02 there is a special case if a start or a repeated start condition is not successful ly generated for i 2 c bus is obstructed by a low level on sda line e.g. a slave device out of bit synchronization, the problem can be solved by transmitting additional clock pulses on the scl line. the i 2 c hardware transmits additional clock pulses when the sta bit is set, but no start condition can be generated because the sda line is pulled low. when the sda line is eventually released, a normal start condition is transmitted, state 08h is entered, and the serial transaction continues. if a repeated start condition is transmitted while sda is obstructed low, the i 2 c hardware also performs the same action as above. in this case, state 08h is entered instead of 10h after a successful start condition is transmitted. note that the software is not involved in so lving these bus problems. the following table is show the status display in i2stat register of i 2 c number and description: master mode slave mode status description status description 0x08 start 0xa0 slave transmit repeat start or stop 0x10 master repea t start 0xa8 slave transmit address ack 0x18 master transmit address ack 0xb0 slave transmit arbitration lost 0x20 master transmit address nack 0xb8 slave transmit data ack 0x28 master transmit data ack 0xc0 slave transmit data nack 0x30 master transmi t data nack 0xc8 slave transmit last data ack 0x38 master arbitration lost 0x60 slave receive address ack 0x40 master receive address ack 0x68 slave receive arbitration lost 0x48 master receive address nack 0x80 slave receive data ack 0x50 master recei ve data ack 0x88 slave receive data nack 0x58 master receive data nack 0x70 gc mode address ack 0x00 bus error 0x78 gc mode arbitration lost 0x90 gc mode data ack 0x98 gc mode data nack 0xf8 bus released note: tatus xf8 exists in both maste r slave modes, and it wont raise interrupt. note: when i2c is enabled and i2c status is entered bus error state, si flag is set by hardware. until the i2c bus error is handled, si flag will maintain its value at 1 and cannot be cleared by software. th at is to
N76E003 datasheet jun 26 , 201 7 page 163 of 267 rev. 1.02 clear si flag does not clear i2c bus error as well. when using si flag to determine i2c status and flow, use following steps to enhance the reliability of the system. solution: C send a stop condition to i2c bus C if the stop condition is invalid, dis able the i2c bus and then restart the communication. for example : while(si != 0) { if (i2stat == 0x00) { sto = 1 ; // check bus status if bus error first send stop } si = 0; if(si!=0) // if si still keep 1 { i2cen = 0 ; // please first disable i2c. i2cen = 1 ; // then enable i2c for clear si. s i = 0 ; i2cen = 0 ; // at last disable i2c for next a new transfer } } 15.4 typical structure of i 2 c in terrupt service routine the following software example in c language for keil tm c51 compiler shows the typical structure of the i 2 c interrupt service routine including the 26 state service routines and may be used as a base for user applications. user can follow or modify it for their own application. if one or more of the five modes are not used, the associated state service routines may be removed, but care should be taken that a deleted routine can never be invoked. v oid i2c_isr (void) interrupt 6 { swi tch (i2stat) { //=============================================== //bus error, always put in isr for noise handling //=============================================== case 0x00: /*00h, bus error occurs*/ sto = 1; //recover from bus error break; //=========== //master mode //===========
N76E003 datasheet jun 26 , 201 7 page 164 of 267 rev. 1.02 case 0x08: /*08h, a start transmitted*/ sta = 0; //sta bit should be cleared by software i2dat = sla_addr1; //load sla+w/r break; case 0x10: /*10h, a repeated start transmitted*/ sta = 0; i2dat = sla_addr2; break; //======================= //master transmitter mode //======================= case 0x18: /*18h, sla+w transmitted, ack received*/ i2dat = next_send_data1; //load data break; case 0x20: /*20h , sla+w transmitted, nack received*/ sto = 1; //transmit stop aa = 1; //ready for ack own sla+w/r or general call break; case 0x28: /*28h, data transmitted, ack received*/ if (conti_tx_data) //if continuing to send data i2dat = nex t_send_data2; else //if no data to be sent { sto = 1; aa = 1; } break; case 0x30: /*30h, data transmitted, nack received*/ sto = 1; aa = 1; break; //=========== //master mode //=========== case 0x38: /*38h, a rbitration lost*/ sta = 1; //retry to transmit start if bus free break; //==================== //master receiver mode //==================== case 0x40: /*40h, sla+r transmitted, ack received*/ aa = 1; //ack next received data bre ak; case 0x48: /*48h, sla+r transmitted, nack received*/
N76E003 datasheet jun 26 , 201 7 page 165 of 267 rev. 1.02 sto = 1; aa = 1; break; case 0x50: /*50h, data received, ack transmitted*/ data_received1 = i2dat; //store received data if (to_rx_last_data1) //if last data will be received aa = 0; //not ack next received data else //if continuing receiving data aa = 1; break; case 0x58: /*58h, data received, nack transmitted*/ data_received_last1 = i2dat; sto = 1; aa = 1; break; //======================= ============= //slave receiver and general call mode //==================================== case 0x60: /*60h, own sla+w received, ack returned*/ aa = 1; break; case 0x68: /*68h, arbitration lost in sla+w/r own sla+w received, a ck returned */ aa = 0; //not ack next received data after //arbitration lost sta = 1; //retry to transmit start if bus free break; case 0x70: / / *70h, general call received, ack returned aa = 1; break; case 0x78: /*78h, arbitration lost in sla+w/r general call received, ack returned*/ aa = 0; sta = 1; break; case 0x80: /*80h, previous own sla+w, data received, ack returned*/ data_received2 = i2dat; if (to_rx_last_data2) a a = 0; else aa = 1; break; case 0x88: /*88h, previous own sla+w, data received,
N76E003 datasheet jun 26 , 201 7 page 166 of 267 rev. 1.02 nack returned, not addressed slave mode entered*/ data_received_last2 = i2dat; aa = 1; //wait for ack next master addressing break; case 0x90: /*90h, previous general call, data received, ack returned*/ data_received3 = i2dat; if (to_rx_last_data3) aa = 0; else aa = 1; break; case 0x98: /*98h, previous general call, data received, nack re turned, not addressed slave mode entered*/ data_received_last3 = i2dat; aa = 1; break; //========== //slave mode //========== cas e 0xa0: /*a0h, stop or repeated start received while still addressed slave mode*/ aa = 1; break; //====================== //slave transmitter mode //====================== cas e 0xa8: /*a8h, own sla+r received, ack returned*/ i2dat = next_send_data3; aa = 1; //when aa is 1, not last data to be //transmitted break; cas e 0xb0: /*b0h, arbitration lost in sla+w/r own sla+r received, ack returned */ i2dat = dummy_data; aa = 0; //when aa is 0, last data to be //transmitted sta = 1; //retry to transmit start if bus free break; cas e 0xb8: /*b8h, previous own sla+r, data transmitted, ack received*/ i2dat = next_send_data4; if (to_tx_last_data) //if last data will be transmitted
N76E003 datasheet jun 26 , 201 7 page 167 of 267 rev. 1.02 aa = 0; else aa = 1; break; cas e 0xc0: /*c0h, previous own sla+r , data transmitted, nack received, not addressed slave mode entered*/ aa = 1; break; cas e 0xc8: /*c8h, previous own sla+r, last data trans - mitted, ack received, not addressed slave aa = 1; mode entered*/ br eak; } //end of switch (i2stat) si = 0; //si should be the last command of i2c isr while(sto); //wait for stop transmitted or bus error //free, sto is cleared by hardware } //end of i2c_isr 15.5 i 2 c time - o ut there is a 14 - bit time - out counter , which can be used to deal with the i 2 c bus hang - up. if the time - out counter is enabled, the counter starts up counting until it overflows. meanwhile i2tof will be set by hardware and requests i 2 c interrupt. when time - out counter is enabled, setting flag si to high will reset counter and restart counting up after si is cleared. if the i 2 c bus hangs up, it causes the si flag not set for a period. the 14 - bit time - out counter will overflow and require the interrupt service. figure 15 - 12 . i 2 c time - o ut counter 1 0 f s y s 1 / 4 1 4 - b i t i 2 c t i m e - o u t c o u n t e r i 2 t o f c l e a r c o u n t e r i 2 t o c e n d i v i 2 c e n s i
N76E003 datasheet jun 26 , 201 7 page 168 of 267 rev. 1.02 i2toc C i 2 c time - out counter 7 6 5 4 3 2 1 0 - - - - - i2tocen div i2tof - - - - - r/w r/w r/w address: bf h reset value : 0000 0000b bit name description 2 i2tocen i 2 c time - out counter enable 0 = i 2 c time - out counter d isabled. 1 = i 2 c time - out counter e nabled. note : please always enable i 2 c interrupt when enable i 2 c time - out counter function 1 div i 2 c time - out counter clock divider 0 = the clock of i 2 c time - out counter is f sys / 1 . 1 = the clock of i 2 c time - out counter is f sys /4 . 0 i2tof i 2 c time - out flag this flag is set by hardware if 14 - bit i 2 c time - out counter overflows. it is cleared by software. 15.6 i 2 c interrupt there are two i 2 c flags, si and i2tof. both of them can generate an i 2 c event interrupt requests. if i 2 c interrupt mask is enabled via setting ei2c (eie.0) and ea as 1, cpu will execute the i 2 c interrupt service routine once any of these two flags is set. user needs to check flags to determine what event caused the int errupt. both of i 2 c flags are cleared by software.
N76E003 datasheet jun 26 , 201 7 page 169 of 267 rev. 1.02 16. pin interrupt the N76E003 provides pin interrupt input for each i/o pin to detect pin state if button or keypad set is used. a maximum 8 - channel pin interrupt detection can be assigned by i/o port sharing. the pin interrupt is generated when any key is pressed on a keyboard or keypad, which produces an edge or level triggering event. pin interrupt may be used to wake the cpu up from idle or power - down mode. each channel of pin interrupt can be enabled and p olarity controlled independently by pipen and pinen register. picon selects which port that the pin interrupt is active. it also defines which type of pin interrupt is us C d C level detect or edge detect. each channel also has its own interrupt flag. there are total eight pin interrupt flags located in pif register. the respective flags for each pin interrupt channel allow the interrupt service routine to poll on which channel on which the interrupt event occurs. all flags in pif register are set by hardware and should be cleared by software. figure 16 - 1 . pin interface block diagram p i n i n t e r r u p t p i f 0 p i n e n 0 p i p e n 0 p i t 0 p i f 1 p i n e n 1 p i p e n 1 p i t 1 p i f 7 p i n e n 7 p i p e n 7 p i t 6 7 p i p s [ 1 : 0 ] ( p i c o n [ 1 : 0 ] ) p 0 . 0 0 1 0 1 0 1 p 1 . 0 p 2 . 0 p 3 . 0 p 0 . 1 p 1 . 1 p 0 . 7 r e s e r v e d p 1 . 7 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 p i n i n t e r r u p t c h a n n e l 0 p i n i n t e r r u p t c h a n n e l 1 p i n i n t e r r u p t c h a n n e l 7 r e s e r v e d r e s e r v e d r e s e r v e d
N76E003 datasheet jun 26 , 201 7 page 170 of 267 rev. 1.02 pin interrupt is generally used to detect an edge transient from peripheral devices like keyboard or keypad. during idle state, the system prefers to enter power - down mode to minimize power consumption and waits for event trigger. pin interrupt can wake up the device from power - down mode . picon C pin interrupt control 7 6 5 4 3 2 1 0 pit67 pit45 pit3 pi t2 pit1 pit0 pips[1:0] r/w r/w r/w r/w r/w r/w r/w address: e9h reset value: 0000 0000b bit name description 7 pit67 pin interr upt channel 6 and 7 type select this bit selects which type that pin interrupt channel 6 and 7 is triggered. 0 = l evel trigger ed. 1 = e dge triggered. 6 pit45 pin interr upt channel 4 and 5 type select this bit selects which type that pin interrupt channel 4 and 5 is triggered. 0 = l evel triggered. 1 = e dge triggered. 5 pit3 pin interrupt channel 3 type select this bit selects wh ich type that pin interrupt channel 3 is triggered. 0 = l evel triggered. 1 = e dge triggered. 4 pit2 pin interrupt channel 2 type select this bit selects which type that pin interrupt channel 2 is triggered. 0 = l evel triggered. 1 = e dge triggered. 3 pit1 pin interrupt channel 1 type select this bit selects which type that pin interrupt channel 1 is triggered. 0 = l evel triggered. 1 = e dge triggered. 2 pit0 pin interrupt channel 0 type select this bit selects which type that pin interrupt channel 0 is tri ggered. 0 = l evel triggered. 1 = e dge triggered. 1:0 pips[:0] pin interrupt port select this field selects which port is active as the 8 - channel of pin interrupt. 00 = port 0. 01 = port 1. 10 = port 2. 11 = port 3.
N76E003 datasheet jun 26 , 201 7 page 171 of 267 rev. 1.02 pinen C pin interrupt negative polarity enable. 7 6 5 4 3 2 1 0 pinen7 pinen6 pinen5 pinen4 pinen3 pinen2 pinen1 pinen0 r/w r/w r/w r/w r/w r/w r/w r/w address: e a h reset value: 0000 0000b bit name description n pinenn pin interrupt cha nnel n negative polarity enable this bit enables low - le vel/falling edge triggering pin interrupt channel n. the level or edge triggered selection depends on each control bit pitn in picon. 0 = l ow - level/falling edge detect disabled . 1 = l ow - level/falling edge detect enabled . pipen C pin interrupt positive pol arity enable. 7 6 5 4 3 2 1 0 pipen7 pipen6 pipen5 pipen4 pipen3 pipen2 pipen1 pipen0 r/w r/w r/w r/w r/w r/w r/w r/w address: e b h reset value: 0000 0000b bit name description n pipenn pin interrupt cha nnel n positive polarity enable this bit enables h igh - level/rising edge triggering pin interrupt channel n. the level or edge triggered selection depends on each control bit pitn in picon. 0 = h igh - level/rising edge detect disabled . 1 = h igh - level/rising edge detect enabled . pif C pin interrupt flags 7 6 5 4 3 2 1 0 pif7 pif6 pif5 pif4 pif3 pif2 pif1 pif0 r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) r (level) r/w (edge) address: e c h reset value: 0000 0 000b bit name description n pifn pin interrupt channel n flag if the edge trigger is selected, this flag will be set by hardware if the channel n of pin interrupt detects an enabled edge trigger. this flag should be cleared by software. if the level trigg er is selected, this flag follows the inverse of the input signals logic level on the channel n of pin interrupt. software cannot control it.
N76E003 datasheet jun 26 , 201 7 page 172 of 267 rev. 1.02 17. pulse width modulate d (pwm) the pwm (pulse width modulation) signal is a useful control solution in wide appl ication field. it can used on motor driving, fan control, backlight brightness tuning, led light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit. the N76E003 pwm is especially designed for motor contr ol by providing three pairs, maximum 1 6 - bit resolution of pwm output with programmable period and duty. the architecture makes user easy to drive the one - phase or three - phase brushless dc motor (bldc), or three - phase ac induction motor. each of six pwm can be configured as one of independent mode, complementary mode, or synchronous mode. if the complementary mode is used, a programmable dead - time insertion is available to protect mos turn - on simultaneously. the pwm waveform can be edge - aligned or center - ali gned with variable interrupt points. 17.1 functional description pwm generator 17.1.1 the pwm generator is clocked by the system clock or timer 1 overflow divided by a pwm clock pre - scalar selectable from 1/1~1/128. the pwm period is defined by effective 1 6 - bit period registers, {pwmph, pwmpl}. the period is the same for all pwm channels for they share the same 1 6 - bit period counter. the duty of each pwm is determined independently by the value of duty registers {pwm0h, pwm0l}, {pwm 1 h, pwm 1 l}, {pwm2h, pwm2l}, {pwm 3 h, p wm 3 l}, {pwm 4 h, pwm 4 l}, and {pwm5h, pwm 5 l }. with six duty registers, six pwm output can be generated independently with different duty cycles. the interval and duty of pwm signal is generated by a 1 6 - bit counter comparing with the period and duty registers. to f acilitate the three - phase motor control, a group mode can be used by setting gp (pwmcon1.5) , which makes {pwm0h, pwm0l} and {pwm 1 h, pwm 1 l} duty register decide duties of the pwm outputs. in a three - phase motor control application, t wo - group pwm output s generally are given the same duty cycle. when the group mode is enabled, {pwm2h, pwm2l} , {pwm 3 h, pwm 3 l} , {pwm 4 h, pwm 4 l} and {pwm5h, pwm5l} registers have no effect. t his mean is {pwm2h, pwm2l} and {pwm 4 h, pwm 4 l} both as same as {pwm0h, pwm0l} . also {pwm 3 h, pwm 3 l} and {pwm5h, pwm5l} are same as {pwm 1 h, pwm 1 l} . note that enabling pwm does not configure the i/o pins into their output mode automatically. user should configure i/o output mode via software manually.
N76E003 datasheet jun 26 , 201 7 page 173 of 267 rev. 1.02 figure 17 - 1 . pwm block diagram the pwm counter generates six pwm signals called pg0 , pg 1, pg2 , pg 3, pg4, and pg 5 . these signals will go through the pwm and fault brake output control circuit. it generates real pwm outputs 1 6 - b i t u p / d o w n c o u n t e r p w m 0 / p 1 . 2 p w m 1 / p 1 . 1 / p 1 . 4 p w m 2 / p 0 . 5 / p 1 . 0 p r e - s c a l a r i n t s e l [ 1 : 0 ] , i n t t y p [ 1 : 0 ] ( p w m c o n 0 [ 3 : 0 ] ) p w m r u n ( p w m c o n 0 . 7 ) c l r p w m ( p w m c o n 0 . 4 ) p w m p r e g i s t e r s l o a d ( p w m c o n 0 . 6 ) p w m f ( p w m c o n 0 . 5 ) p w m p b u f f e r p w m 0 b u f f e r p w m 0 r e g i s t e r 0 - t o - 1 p w m a n d f a u l t b r a k e o u t p u t c o n t r o l p w m t y p ( p w m c o n 1 . 4 ) e d g e / c e n t e r i n t e r r u p t s e l e c t / t y p e p w m d i v 0 [ 2 : 0 ] ( p w m c o n 1 [ 2 : 0 ] ) p g 0 p w m i n t e r r u p t b r a k e e v e n t ( p 1 . 4 / f b ) 0 1 t i m e r 1 o v e r f l o w p w m c k s ( c k c o n . 6 ) f p w m = c o u n t e r m a t c h i n g ( e d g e a l i g n e d ) / u n d e r f l o w ( v e n t e r a l i g n e d ) f s y s c l e a r c o u n t e r = p w m 1 b u f f e r p w m 1 r e g i s t e r p g 1 = p w m 2 b u f f e r p w m 2 r e g i s t e r = p w m 3 b u f f e r p w m 3 r e g i s t e r = p w m 4 b u f f e r p w m 4 r e g i s t e r = p w m 5 b u f f e r p w m 5 r e g i s t e r = p g 2 p g 3 p g 4 p g 5 0 1 0 1 0 1 0 1 g p ( p w m c o n 1 . 5 ) ( p w m p h , p w m p l ) ( p w m 0 h , p w m 0 l ) ( p w m 1 h , p w m 1 l ) ( p w m 2 h , p w m 2 l ) ( p w m 3 h , p w m 3 l ) ( p w m 4 h , p w m 4 l ) ( p w m 5 h , p w m 5 l ) p w m 3 / p 0 . 0 / p 0 . 4 p w m 4 / p 0 . 1 p w m 5 / p 0 . 3 / p 1 . 5
N76E003 datasheet jun 26 , 201 7 page 174 of 267 rev. 1.02 o n i/o pins. the output control circuit determines the pwm mode, dead - time insertion, mask output, fault brake control, and pwm polarity. the last stage is a multiplexer of pwm output or i/o function. user should set the pion bit to make the correspond ing p in function as pwm output. meanwhile, the general purpose i/o function can be used. figure 17 - 2 . pwm and fault brake output control block diagram user should follow the initiali zation steps below to start generating the pwm signal output. in the first step by setting clrpwm (pwmcon0.4), it ensures the 1 6 - bit up counter reset for the accuracy of the first duration. after initialization and setting {pwmph, pwmpl} and all {pwmnh, pw mnl} registers, pwmrun (pwmcon0.7) can be set as logic 1 to trigger the 1 6 - bit counter running. pwm starts to generate waveform on its output pins. the hardware for all period and duty control registers are double buffered designed. therefore, {pwmph, pwmp l} and all {pwmnh, pwmnl} registers can be p g 0 p g 1 p g 2 p g 3 p g 4 p g 5 f b i n e n ( p w m c o n 1 . 3 ) p w m a n d f a u l t b r a k e o u t p u t c o n t r o l p w m m o d e s e l e c t p w m m o d [ 1 : 0 ] ( p w m c o n 1 [ 7 : 6 ] ) d e a d t i m e i n s e r t i o n p d t e n , p d t c n t m a s k o u t p u t p m d 0 p m e n 0 p m d 1 p m e n 1 b r a k e c o n t r o l p w m p o l a r i t y b r a k e e v e n t ( p 1 . 4 / f b ) p g 0 _ d t p g 1 _ d t p w m 0 / 1 m o d e p w m 0 / 1 d e a d t i m e f b d 0 f b d 1 p n p 0 p n p 1 p m d 2 p m e n 2 p m d 3 p m e n 3 p g 2 _ d t p g 3 _ d t p w m 2 / 3 m o d e p w m 2 / 3 d e a d t i m e f b d 2 f b d 3 p n p 2 p n p 3 p m d 4 p m e n 4 p m d 5 p m e n 5 p g 4 _ d t p g 5 _ d t p w m 4 / 5 m o d e p w m 4 / 5 d e a d t i m e f b d 4 f b d 5 p n p 4 p n p 5 b r k 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 p m e n , p m d f b d p n p p 1 . 2 p i o 0 0 0 1 p 1 . 1 p i o 0 1 0 1 p 1 . 4 p i o 1 1 0 1 p 0 . 5 p i o 0 2 0 1 p 1 . 0 p i o 1 2 0 1 p 0 . 0 p i o 0 3 0 1 p 0 . 4 p i o 1 3 0 1 p 0 . 1 p i o 0 4 0 1 p 0 . 3 p i o 0 5 0 1 p 1 . 5 p i o 1 5 0 1 p w m 0 / p 1 . 2 p w m 1 / p 1 . 1 p w m 2 / p 0 . 5 p w m 3 / p 0 . 0 p i o c o n 1 , p i o c o n 0 p w m & i / o s w i t c h p w m 1 / p 1 . 4 p w m 2 / p 1 . 0 p w m 3 / p 0 . 4 p w m 5 / p 0 . 3 p w m 5 / p 1 . 5 p w m 4 / p 0 . 1
N76E003 datasheet jun 26 , 201 7 page 175 of 267 rev. 1.02 written to at any time, but the period and duty cycle of pwm will not be updated immediately until the l oad (pwmcon0.6) is set and previous period is complete. this prevents glitches when updating the pwm period o r duty. a loading of new period and duty by setting load should be ensured complete by monitoring it and waiting for a hardware automatic clearing load bit. any updating of pwm control registers during load bit as logic 1 will cause unpredictable output. p wmcon0 C pwm control 0 (bit - addressable) 7 6 5 4 3 2 1 0 pwmrun load pwmf clrpwm - - - - r/w r/w r/w r/w - - - - address: d8h reset value: 0000 0000b bit name description 7 pwmrun pwm run enable 0 = pwm stays in idle. 1 = pwm starts running. 6 load pw m new period and duty load this bit is used to load period and duty control registers in their buffer if new period or duty value needs to be updated. the loading will act while a pwm period is completed. the new period and duty affect ed on the next pwm cy cle. after the loading is complete, load will be automatically cleared via hardware. the meaning of writing and reading load bit is different. writing: 0 = no effect. 1 = load new period and duty in their buffers while a pwm period is completed. reading: 0 = a loading of new period and duty is finished. 1 = a loading of new period and duty is not yet finished. 5 pwmf pwm flag this flag is set according to definitions of intsel[ 2 :0] and inttyp[1:0] in pwm intc . this bit is cleared by software. 4 clrpwm c lear pwm counter setting this bit clears the value of pwm 1 6 - bit counter for resetting to 0 000h. after the counter value is cleared, clrpwm will be automatically cleared via hardware. the meaning of writing and reading clrpwm bit is different. writing: 0 = no effect. 1 = clearing pwm 1 6 - bit counter. reading: 0 = pwm 1 6 - bit counter is completely cleared. 1 = pwm 1 6 - bit counter is not yet cleared.
N76E003 datasheet jun 26 , 201 7 page 176 of 267 rev. 1.02 pwmcon1 C pwm control 1 7 6 5 4 3 2 1 0 pwmmod[1:0] gp pwmtyp fbinen pwmdiv[2:0] r/w r/w r/w r/w r/w addr ess: dfh reset value: 0000 0000b bit name description 5 gp group mode enable this bit enables the group mode. if enabled, the duty of first three pairs of pwm are decided by pwm01h and pwm01l rather than their original duty control registers. 0 = group mo de disabled. 1 = group mode enabled. 2:0 pwmdiv[2:0] pwm clock divider this field decides the pre - scale of pwm clock source. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. ckcon C clock control 7 6 5 4 3 2 1 0 - pwmcks - t1m t0m - cloen - - r/w - r/w r/w - r/w - address: 8eh reset value: 0000 0000b bit name description 6 pwmcks pwm clock source select 0 = the clock source of pwm is the system clock f sys . 1 = the clock source of pwm is the overflow of timer 1. pwmpl C pwm period low byte 7 6 5 4 3 2 1 0 pwmp[7:0] r/w address: d9h reset value: 0000 0000b bit name description 7:0 pwmp[7:0] pwm period low byte this byte with pwmph controls the period of the pwm generator signal.
N76E003 datasheet jun 26 , 201 7 page 177 of 267 rev. 1.02 pwmph C pwm period high byt e 7 6 5 4 3 2 1 0 pwmp[1 5 :8] r/w address: d1h reset value: 0000 0000b bit name description 7 :0 pwmp[1 5 :8] pwm period high byte this byte with pwmpl controls the period of the pwm generator signal. pwm0l C pwm0 duty low byte 7 6 5 4 3 2 1 0 pwm0[7:0] r/w address: dah reset value: 0000 0000b bit name description 7:0 pwm0[7:0] pwm0 duty low byte this byte with pwm0h controls the duty of the output signal p g 0 from pwm generator . pwm0h C pwm0 duty high byte 7 6 5 4 3 2 1 0 pwm0 [15:8] r/w address: d2 h reset value: 0000 0000b bit name description 7 :0 pwm0[1 5 :8] pwm0 duty high byte this byte with pwm0 l controls the duty of the output signal p g 0 from pwm generator . pwm1l C pwm/1 duty low byte 7 6 5 4 3 2 1 0 pwm1[7:0] r/w address: d b h reset value: 0 000 0000b bit name description 7:0 pwm1[7:0] pwm 1 duty low byte this byte with pwm 1 h controls the duty of the output signal p g1 from pwm generator .
N76E003 datasheet jun 26 , 201 7 page 178 of 267 rev. 1.02 pwm1h C pwm1 duty high byte 7 6 5 4 3 2 1 0 pwm1 [15:8] r/w address: d 3 h reset value: 0000 0000b bit nam e description 7 :0 pwm1 [15:8] pwm 1 duty high byte this byte with pwm 1l controls the duty of the output signal p g1 from pwm generator . pwm2l C pwm2 duty low byte 7 6 5 4 3 2 1 0 pwm2[7:0] r/w address: d c h reset value: 0000 0000b bit name description 7: 0 pwm2[7:0] pwm 2 duty low byte this byte with pwm 2 h controls the duty of the output signal p g2 from pwm generator . pwm2h C pwm2 duty high byte 7 6 5 4 3 2 1 0 pwm2[1 5 :8] r/w address: d 4 h reset value: 0000 0000b bit name description 7 :0 pwm2[1 5 :8] pwm 2 duty high byte this byte with pwm 2l controls the duty of the output signal p g2 from pwm generator . pwm 3 l C pwm 3 duty low byte 7 6 5 4 3 2 1 0 pwm 3 [7:0] r/w address: d d h reset value: 0000 0000b bit name description 7:0 pwm 3 [7:0] pwm 3 duty low byte thi s byte with pwm 3 h controls the duty of the output signal p g 3 from pwm generator .
N76E003 datasheet jun 26 , 201 7 page 179 of 267 rev. 1.02 pwm 3 h C pwm 3 duty high byte 7 6 5 4 3 2 1 0 pwm 3 [15:8] r/w address: d 5 h reset value: 0000 0000b bit name description 7 :0 pwm 3 [15:8] pwm 3 duty high byte this byte with pwm 3 l controls the duty of the output signal p g 3 from pwm generator . pwm4l C pwm4 duty low byte 7 6 5 4 3 2 1 0 pwm4[7:0] r/w address: cc h , page:1 reset value: 0000 0000b bit name description 7:0 pwm4[7:0] pwm 4 duty low byte this byte with pwm 4 h controls the duty of the output signal p g4 from pwm generator . pwm4h C pwm4 duty high byte 7 6 5 4 3 2 1 0 pwm4[1 5 :8] r/w address: c4 h , page:1 reset value: 0000 0000b bit name description 7 :0 pwm4[1 5 :8] pwm 4 duty high byte this byte with pwm 4l controls the du ty of the output signal p g4 from pwm generator . pwm 5 l C pwm 5 duty low byte 7 6 5 4 3 2 1 0 pwm 5 [7:0] r/w address: c dh , page:1 reset value: 0000 0000b bit name description 7:0 pwm 5 [7:0] pwm 5 duty low byte this byte with pwm 5 h controls the duty of the o utput signal p g 5 from pwm generator .
N76E003 datasheet jun 26 , 201 7 page 180 of 267 rev. 1.02 pwm 5 h C pwm 5 duty high byte 7 6 5 4 3 2 1 0 pwm 5 [15:8] r/w address: c5 h , page:1 reset value: 0000 0000b bit name description 7 :0 pwm 5 [15:8] pwm 5 duty high byte this byte with pwm 5 l controls the duty of the output s ignal p g 5 from pwm generator . pio con0 C pwm or i/o select 7 6 5 4 3 2 1 0 - - pio 0 5 pio 0 4 pio 0 3 pio 0 2 pio 0 1 pio 0 0 - - r/w r/w r/w r/w r/w r/w address: deh reset value: 0000 0000b bit name description 5 pio 0 5 p0. 3 /pwm5 pin function select 0 = p0. 3 /pwm5 pin functions as p0. 3 . 1 = p0. 3 /pwm5 pin functions as pwm5 output. 4 pio 0 4 p 0 .1 /pwm4 pin function select 0 = p 0 .1 /pwm4 pin functions as p 0 .1 . 1 = p 0 .1 /pwm4 pin functions as pwm4 output. 3 pio 0 3 p0. 0 /pwm3 pin function select 0 = p0. 0 /pwm3 pin functions a s p0. 0 . 1 = p0. 0 /pwm3 pin functions as pwm3 output. 2 pio 0 2 p 1.0 /pwm2 pin function select 0 = p 1 . 0 /pwm2 pin functions as p 1 . 0 . 1 = p 1 . 0 /pwm2 pin functions as pwm2 output. 1 pio 0 1 p1.1/pwm1 pin function select 0 = p1.1/pwm1 pin functions as p1.1. 1 = p1.1 /pwm1 pin functions as pwm1 output. 0 pio 0 0 p1. 2 /pwm0 pin function select 0 = p1. 2 /pwm0 pin functions as p1. 2 . 1 = p1. 2 /pwm0 pin functions as pwm0 output. pio con1 C pwm or i/o select 7 6 5 4 3 2 1 0 - - pio 1 5 - pio 1 3 pio 1 2 pio 1 1 - - - r/w - r/w r/w r/w - address: c6 h , page:1 reset value: 0000 0000b bit name description 5 pio 1 5 p 1 . 5 /pwm5 pin function select 0 = p 1 . 5 /pwm5 pin functions as p 1 . 5 . 1 = p 1 . 5 /pwm5 pin functions as pwm5 output.
N76E003 datasheet jun 26 , 201 7 page 181 of 267 rev. 1.02 bit name description 3 pio 1 3 p0. 4 /pwm3 pin function select 0 = p0. 4 /pwm3 pin functions as p0. 4 . 1 = p0. 4 /pwm3 pin functions as pwm3 output. 2 pio 1 2 p 0 . 5 /pwm2 pin function select 0 = p0. 5 /pwm2 pin functions as p0. 5 . 1 = p0. 5 /pwm2 pin functions as pwm2 output. 1 pio 1 1 p1. 4 /pwm1 pin function select 0 = p1. 4 /pwm1 pin functions as p1. 4 . 1 = p1 . 4 /pwm1 pin functions as pwm1 output. pwm types 17.1.2 the pwm generator provides two pwm types: edge - aligned or center - aligned. pwm type is selected by pwmtyp (pwmcon1.4). pwmcon1 C pwm control 1 7 6 5 4 3 2 1 0 pwmmod[1:0] gp pwmtyp fbinen pwmdiv[2:0] r/w r/ w r/w r/w r/w address: dfh reset value: 0000 0000b bit name description 4 pwmtyp pwm type select 0 = edge - aligned pwm. 1 = center - aligned pwm. 17.1.2.1 edge - aligned type in edge - aligned mode, the 1 6 - bit counter use s single slop operation by counting up from 0 000 h to {pwmph, pwmpl} and then starting from 0 000h. the pwm generator signal (pgn before pwm and fault brake output control) is cleared on the compare match of 1 6 - bit counter and the duty register {pwmnh, pwmnl} and set at the 1 6 - bit counter is 0 000h. the re sult pwm output waveform is left - edge aligned.
N76E003 datasheet jun 26 , 201 7 page 182 of 267 rev. 1.02 figure 17 - 3 . pwm edge - aligned type waveform the output frequency and duty cycle for edge - aligned pwm are given by following equatio ns: pwm frequency = (f pwm is the pwm clock source frequency divided by pwmdiv). pwm high level duty = . 17.1.2.2 center - aligned type in center - aligned mode, the 1 6 - bit counter use dual slop operation by counting up from 0 000h to {pwmph, pwmpl} and then counting down from {pwmph, pwmpl} to 0 000h. the pgn signal is cleared on the up - count compare match of 1 6 - bit counter and the duty register {pwmnh, pwmnl} and set on the down - count compare match. center - aligned pwm may be u sed to generate non - overlapping waveforms. p w m p ( 2 n d ) p w m p ( 1 s t ) p w m 0 1 ( 2 n d ) p w m 0 1 ( 1 s t ) p g 0 1 o u t p u t l o a d p w m 0 1 ( 2 n d ) l o a d p w m p ( 2 n d ) p w m 0 1 ( 2 n d ) d u t y v a l i d p w m p ( 2 n d ) p e r i o d v a l i d 1 2 - b i t c o u n t e r 1 } pwmpl , pwmph { f pwm ? 1 } pwmpl , pwmph { } pwmnl , pwmnh { ?
N76E003 datasheet jun 26 , 201 7 page 183 of 267 rev. 1.02 figure 17 - 4 . pwm center - aligned type waveform the output frequency and duty cycle for center - aligned pwm are given by following equatio ns: pwm frequency = (f pwm is the pwm clock source frequency divided by pwmdiv). pwm high level duty = . operation modes 17.1.3 after pgn signals pass through the first stage of the pwm and fault brake output control ci rcuit. the pwm mode selection circuit generates different kind of pwm output modes with six - channel, three - pair signal pg0~pg 5 . it supports independent mode, complementary mode, and synchronous mode. p w m p ( 2 n d ) p w m p ( 1 s t ) p w m 0 1 ( 2 n d ) p w m 0 1 ( 1 s t ) p g 0 1 o u t p u t l o a d p w m 0 1 ( 2 n d ) l o a d p w m p ( 2 n d ) p w m 0 1 ( 2 n d ) d u t y v a l i d p w m p ( 2 n d ) p e r i o d v a l i d 1 2 - b i t c o u n t e r } pwmpl , pwmph { 2 f pwm } pwmpl , pwmph { } pwmnl , pwmnh {
N76E003 datasheet jun 26 , 201 7 page 184 of 267 rev. 1.02 pwmcon1 C pwm control 1 7 6 5 4 3 2 1 0 pwmmod[1:0] gp pwmtyp fbinen pwmdiv[2:0] r/w r/w r/w r/w r/w address: dfh reset value: 0000 0000b bit name description 7:6 pwmmod[1:0] pwm mode select 00 = independent mode. 01 = complementary mode. 10 = synchronized mode. 11 = reserved. 17.1.3.1 independent mode independent mode is enabled when pwmmod[1:0] (pwmcon1[7:6]) is [0:0]. it is the default mode of pwm. pg0 , pg1, pg 2 , pg3, pg 4 and pg5 output pwm signals independently . 17.1.3.2 complementary mode with dead - time insertion complementary mode is enabled when pwmmod[1:0] = [0:1]. in this mode, pg0/2/4 output pwm signals the same as the independent mode. however, pg1/3/5 output the out - phase pwm signals of pg0/2/4 correspondingly , a nd ignore pg1/3/5 d uty register {pwmnh, pwmnl} (n:1/3/5) . this mode makes pg0/pg1 a pwm complementary pair and so on pg2/pg3 and pg4/pg5. n a real motor application, a complementary pw output always has a need of dead - time insertion to prevent damage of the power switching device like gpibs due to being active on simultaneously of the upper and lower switches of the half bridge, even in a s duration. for a power switch device physically cannot switch on/off instantly. for the N76E003 pwm, each pwm pair share a 9 - bit dead - time down - counter pdtcnt used to produce the off time between two pwm signals i n the same pair. on implementation, a 0 - to - 1 signal edge delays after pdtcnt timer underflows. the timing diagram illustrates the complementary mode with dead - time insertion of pg0/pg1 pair. pairs of pg2/pg3 and pg4/pg5 have the same dead - time circuit. eac h pair has its own dead - time enabling bit in the field of pdten[3:0]. note that the pdtcnt and pdten registers are all ta write protection. the dead - time control are also valid only when the pwm is configured in its complementary mode.
N76E003 datasheet jun 26 , 201 7 page 185 of 267 rev. 1.02 figure 17 - 5 . pwm complementary mode with dead - time insertion pdten C pwm dead - time enable ( ta protected ) 7 6 5 4 3 2 1 0 - - - pdtcnt.8 - pdt45en pdt23en pdt01en - - - r/w - r/w r/w r/w address: f9h reset value: 0000 0000b bit name description 4 pdtcnt.8 pwm dead - time counter bit 8 see pdtcnt register. 2 pdt45en pwm4/5 pair dead - time insertion enable this bit is valid only when pwm4/5 is under complementary mode. 0 = no delay on gp4/gp5 pair si gnals. 1 = insert dead - time delay on the rising edge of gp4/gp5 pair signals. 1 pdt23en pwm2/3 pair dead - time insertion enable this bit is valid only when pwm2/3 is under complementary mode. 0 = no delay on gp2/gp3 pair signals. 1 = insert dead - time delay on the rising edge of gp2/gp3 pair signals. 0 pdt01en pwm0/1 pair dead - time insertion enable this bit is valid only when pwm0/1 is under complementary mode. 0 = no delay on gp0/gp1 pair signals. 1 = insert dead - time delay on the rising edge of gp0/gp1 pa ir signals. p g 0 p g 1 p g 0 _ d t p g 1 _ d t
N76E003 datasheet jun 26 , 201 7 page 186 of 267 rev. 1.02 pdtcnt C pwm dead - time counter ( ta protected ) 7 6 5 4 3 2 1 0 pdtcnt[7:0] r/w address: fah reset value: 0000 0000b bit name description 7:0 pdtcnt[7:0] pwm dead - time counter low byte this 8 - bit field combined with pdten.4 forms a 9 - bit pwm dead - time counter pdtcnt. this counter is valid only when pwm is under complementary mode and the correspond pdten bit for pwm pair is set. pwm dead - time = . note that user should not modify pdtcnt during pwm run time. 17.1.3.3 synchronous m ode synchronous mode is enabled when pwmmod[1:0] = [1:0]. in this mode, pg0/2/4 output pwm signals the same as the independent mode. pg1/3/5 output just the same in - phase pwm signals of pg02/4 correspondingly. mask output control 17.1.4 each pwm signal can be sof tware masked by driving a specified level of pwm signal. the pwm mask output function is quite useful when controlling electrical commutation motor like a bldc. pmen contains six bits, those determine which channel of pwm signal will be masked. pmd set the individual mask level of each pwm channel. the default value of pmen is 00h, which makes all outputs of pwm channels follow signals from pwm generator. note that the masked level is reversed or not by pnp setting on pwm output pins. pmen C pwm mask enable 7 6 5 4 3 2 1 0 - - pmen5 pmen4 pmen3 pmen2 pmen1 pmen0 - - r/w r/w r/w r/w r/w r/w address: fbh reset value: 0000 0000b bit name description n pmenn pwmn mask enable 0 = pwmn signal outputs from its pwm generator. 1 = pwmn signal is masked by pmdn. sys f 1 pdtcnt ?
N76E003 datasheet jun 26 , 201 7 page 187 of 267 rev. 1.02 pmd C pwm mask data 7 6 5 4 3 2 1 0 - - pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 - - r/w r/w r/w r/w r/w r/w address: fch reset value: 0000 0000b bit name description n pmdn pwmn mask data the pwmn signal outputs mask data once its corresponding pmenn is set. 0 = pwmn signal is masked by 0 . 1 = pwmn signal is masked by 1 . fault brake 17.1.5 the fault brake function is usually implemented in conjunction with an enhanced pwm circuit. it rules as a fault detection input to protect the motor system from damage. fault brake pin input (fb) is valid when fbinen (pwmcon1.3) is set. when fault brake is asserted pwm signals will be individually overwritten by fbd corresponding bits. pwmrun (pwmcon0.7) will also be automatically cleared by hardware to stop pwm generating. the pwm 1 6 - bit counter will also be reset as 0 000h. a indicating flag fbf will be set by hardware to assert a fault brake interrupt if enabled. fbd data output remains even after the fbf is cleared by software. user should resume the pwm output only by setting pwmr un again. meanwhile the fault brake state will be released and pwm waveform outputs on pins as usual. fault brake input has a polarity selection by fbinls (fbd.6) bit. note that the fault brake signal feed in fb pin should be longer than eight - system - clock time for fb pin input has a permanent 8/f sys de - bouncing, which avoids fake fault brake event by input noise. the other path to trigger a fault brake event is the adc compare event. it asserts the fault brake behavior just the same as fb pin input. see se ctor 18.1.3 adc c onversion result comparator on page 193 . figure 17 - 6 . fault brake function block diagram f b i n e n f b ( p 1 . 4 ) a d c c o m p a r a t o r a d c c o m p a r e e v e n t f a u l t b r a k e e v e n t d e - b o u n c e 0 1 f b i n l s f b f f a u l t b r a k e i n t e r r u p t
N76E003 datasheet jun 26 , 201 7 page 188 of 267 rev. 1.02 pwmcon1 C pwm control 1 7 6 5 4 3 2 1 0 pwmmod[1:0] gp pwmtyp fbinen pwmdiv[2:0] r/w r/w r/w r/w r/w address: dfh reset value: 0000 0000b bit name description 3 fbinen fb pin input enable 0 = pwm output f ault braked by fb pin input disabled. 1 = pwm output fault braked by fb pin input enabled. once an edge, which matches fbinls (fbd.6) selection, occurs on fb pin, pwm0~5 output fault brake data in fbd register and pwm6/7 remains their states. pwmrun (pwmco n0.7) will also be automatically cleared by hardware. the pwm output resumes when pwmrun is set again. fbd C pwm fault brake data 7 6 5 4 3 2 1 0 fbf fbinls fbd5 fbd4 fbd3 fbd2 fbd1 fbd0 r/w r/w r/w r/w r/w r/w r/w r/w address: d7h reset value: 0000 00 00b bit name description 7 fbf fault brake flag this flag is set when fbinen is set as 1 and fb pin detects an edge, which matches fbinls (fbd.6) selection . this bit is cleared by software. after fbf is cleared, fault brake data output will not be release d until pwmrun (pwmcon0. 7 ) is set. 6 fbinls fb pin input level selection 0 = falling edge. 1 = rising edge. n fb dn pwmn fault brake data 0 = pwmn signal is overwritten by 0 once fault brake asserted . 1 = pwmn signal is overwritten by 1 once fault brake a sserted . polarity control 17.1.6 each pwm output channel has its independent polarity control bit, pnp0~pnp 5 . the default is high active level on all control fields implemented with positive logic. it means the power switch is on when pwm outputs high level and off when low level. user can easily configure all setting with positive logic and then set pnp bit to make pwm actually outputs according to the negative logic.
N76E003 datasheet jun 26 , 201 7 page 189 of 267 rev. 1.02 pnp C pwm negative polarity 7 6 5 4 3 2 1 0 - - pnp5 pnp4 pnp3 pnp2 pnp1 pnp0 - - r/w r/w r/w r/w r/w r/w address: d6h reset value: 0000 0000b bit name description n pnp n pwmn negative polarity output enable 0 = pwmn signal outputs directly on pwmn pin. 1 = pwmn signal outputs inversely on pwmn pin. 17.2 pwm interrupt the pwm module has a flag pwmf (pwmcon0.5) to indicate certain point of each complete pwm period. the indicating pwm channel and point can be selected by intsel[ 2 :0] and inttyp[1:0] ( pwm intc [ 2 : 0 ] and [ 5 : 4 ]). note that the center point and the end point interrupts are only available when pwm operates in its center - aligned type. pwmf is cleared by software. pwm intc C pwm interrupt control 7 6 5 4 3 2 1 0 - - inttyp1 inttyp0 - intsel 2 intsel1 intsel0 - - r/w r/w - r/w r/w r/w address: b 7 h , page : 1 reset value: 0000 0000b bit name descript ion 5 : 4 inttyp[1:0] pwm interrupt type select these bit select pwm interrupt type. 00 = falling edge on pwm0 /1 /2 /3 /4 /5 pin. 01 = rising edge on pwm0 /1 /2 /3 /4 /5 pin. 10 = central point of a pwm period. 11 = end point of a pwm period. note that the central p oint interrupt or the end point interrupt is only available while pwm operates in center - aligned type. 2 :0 intsel[ 2 :0] pwm interrupt pair select these bits select which pwm channel asserts pwm interrupt when pwm interrupt type is selected as falling or ri sing edge on pwm0/ 1/ 2/ 3/ 4 /5 pin.. 0 00 = pwm0. 0 01 = pwm 1 . 0 10 = pwm 2 . 011 = pwm3 . 100 = pwm4 . 101 = pwm5 . o thers = pwm0. the pwm interrupt related with pwm waveform is shown as figure below.
N76E003 datasheet jun 26 , 201 7 page 190 of 267 rev. 1.02 figure 17 - 7 . pwm interrupt type fault brake event requests another interrupt, fault brake interrupt. it has different interrupt vector from pwm interrupt. when either fault brake pin input event or adc compare event occurs, fbf (fbd.7) will be set by hardware. it generates fault brake interrupt if enabled. the fault brake interrupt enable bit is efb (eie.5). fbf is cleared via software. r e s e r v e d p w m f ( c e n t r a l p o i n t ) ( i n t t y p [ 1 : 0 ] = [ 1 : 0 ] ) p w m f ( e n d p o i n t ) ( i n t t y p [ 1 : 0 ] = [ 1 : 1 ] ) c e n t r a l p o i n t e n d p o i n t p w m 0 / 2 / 4 p i n o u t p u t s o f t w a r e c l e a r 1 2 - b i t p w m c o u n t e r d e a d t i m e p w m f ( f a l l i n g e d g e ) ( i n t t y p [ 1 : 0 ] = [ 0 : 0 ] ) p w m f ( r i s i n g e d g e ) ( i n t t y p [ 1 : 0 ] = [ 0 : 1 ] ) e d g e - a l i g n e d p w m c e n t e r - a l i g n e d p w m r e s e r v e d
N76E003 datasheet jun 26 , 201 7 page 191 of 267 rev. 1.02 18. 12 - bit analog - to - digital convert e r (adc) the N76E003 is embedded with a 12 - bit sar adc. the adc ( analog - to - digital converter ) allows conversion of an analog input signal to a 12 - bit binary representation of that signal. the N76E003 is selected as 8 - c hannel inputs in single end mode . the internal band - gap voltage also can be the internal adc input. the analog in put , multiplexed into one sample and hold circuit, charges a sample and hold capacitor. the output of the sample and hold capacitor is the input into the converter. the converter then generates a digital result of this analog level via successive approxima tion and stores the result in the result register s . 18.1 functional description adc operation 18.1.1 figure 18 - 1 . 12 - bit adc block diagram 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 a i n 0 a i n 1 a i n 2 a i n 3 a i n 4 a i n 5 a i n 6 a i n 7 i n t e r n a l b a n d - g a p a d c h s [ 3 : 0 ] 1 2 - b i t s a r a d c a / d c o n v e r t i o n s t a r t a d c r h a d c r l 1 2 a d c f a d c i n t e r r u p t a d c r e s u l t c o m p a r a t o r v r e f v d d a d c e n a d c s s t a d c p x 0 1 p 0 . 4 p 1 . 3 e t g t y p [ 1 : 0 ] ( a d c c o n 1 [ 3 : 2 ] ) [ 0 0 ] [ 0 1 ] [ 1 0 ] [ 1 1 ] 0 0 0 1 1 0 e t g s e l [ 1 : 0 ] ( a d c c o n 0 [ 5 : 4 ] ) p w m 0 p w m 2 p w m 4 a d c d l y e x t e r n a l t r i g g e r 1 1 s t a d c a d c e x
N76E003 datasheet jun 26 , 201 7 page 192 of 267 rev. 1.02 before adc operation, the adc circuit should be ena bled by setting adcen (adccon 1 .0). this make s adc circuit active. it consume extra power. once adc is not used, clearing adcen to turn off adc circuit saves power. the adc analog input pin should be specially considered. adchs[ 2 :0] are channel selection b its that control which channel is connected to the sample and hold circuit. user needs to configure selected adc input pins as input - only (high impedance) mode via respective bits in p x m n registers . this configuration disconnects the digital output circuit of each selected adc input pin. but the digital input circuit still works . digital input may cause the input buffer to induce leakage current. to disable the digital input buffer, the respective bits in ain di d s should be set. configuration above makes sel ected adc analog input pins pure analog inputs to allow external feeding of the analog voltage signals. also, t he adc clock rate needs to be considered carefully. the adc maximum clock frequency is listed in table 31 - 9 . adc electrical cha racteristics clock above the maximum clock frequency degrades adc performance unpredictably. an a/d conversion is initiated by setting the adcs bit (adccon 0 . 6 ). when the conversion is complete, the hardware will clear adcs automatically, set adc f ( adccon0.7 ) and generate an interrupt if enabled. the new conversion result will also be stored in adc r h (most significant 8 bits) and adc r l (least significant 4 bits) . the 12 - bit adc result value is . by the way, digital circuitry ins ide and outside the device generates noise which might affect the accuracy of adc measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. keep analog signal paths as short as possible. make sure to run analog signals tracks well away from high - speed digital tracks. 2. place the device in idle mode during a conversion. 3. if any ain pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. ad c conversion triggered by external source 18.1.2 besides setting adcs via software, the N76E003 is enhanced by supporting hardware triggering method to start an a/d conversion. if adcex (adccon 1 .1) is set, edges or period points on selected pwm channel or edges o f stadc pin will automatically trigger an a/d conversion. ( the hardware trigger also set s adcs by hardware.) for application flexibility, stadc pin can be exchanged by stadc px ( adccon1 . 6 ). ref ain v v 4095
N76E003 datasheet jun 26 , 201 7 page 193 of 267 rev. 1.02 the effective condition is selected by e tg sel (adccon0[5:4]) and e t g typ (adccon1[ 3 : 2 ]). a trigger delay can also be inserted between external trigger point and a/d conversion. the external trigging adc hardware with controllable trigger delay makes the N76E003 feasible for high performance motor control. note that during adc is busy in converting (adcs = 1) , any conversion triggered by software or hardware will be ignored and there is no warning presented. figure 18 - 2 . external triggering adc cir cuit adc c onversion result comparator 18.1.3 the N76E003 adc has a digital comparator, which compares the a/d conversion result with a 12 - bit constant value given in acmph and acmpl registers. the adc comparator is enabled by setting adcmpen (adccon2.5) and each compare will be done on every a/d conversion complete moment. adcmpo (adccon2.4) shows the compare result according to its output polarity setting bit adcmpop (adccon2.6) . the adc comparing result can trigger a pwm fault brake output directly. this functio n is enabled when ad fb en (adccon2.7) . when adcmpo is set, it generates a adc compar e event and asserts fault brake . please also see sector 18.1.5 fault brake on page 129 . figure 18 - 3 . adc result comparator e t g t y p [ 1 : 0 ] ( a d c c o n 1 [ 3 : 2 ] ) [ 0 0 ] [ 0 1 ] [ 1 0 ] [ 1 1 ] 0 0 0 1 1 0 e t g s e l [ 1 : 0 ] ( a d c c o n 0 [ 5 : 4 ] ) p w m 0 p w m 2 p w m 4 a d c d l y e x t e r n a l t r i g g e r 1 1 s t a d c a d c r [ 1 1 : 0 ] a d c m p [ 1 1 : 0 ] + - a d c m p o ( a d c c o n 2 . 4 ) 0 1 a d f b e n ( a d c c o n 2 . 7 ) a d c c o m p a r e e v e n t a d c m p o p ( a d c c o n 2 . 6 ) a d c m p e n ( a d c c o n 2 . 5 )
N76E003 datasheet jun 26 , 201 7 page 194 of 267 rev. 1.02 internal band - gap 18.1.4 at room temperature, all N76E003 band - gap voltage values will be calibrated within the range of 1.17v to 1. 30 v. if you want to get the actual band - gap value for N76E003, read the 2 by tes value after the uid a ddress and the actually valid bit is 12. the first byte is the upper 8 bits, and the lower 4 bits of the second byte are the lower 4 bits of the 12 bit. reading and calculation steps: 1. read a bad - gap value with iap by reading uid; 2. merge the upper 8 bits and the lower 4 bits; 3. use the following formula to convert to an actual voltage value. formula as following for example: read the 2 bytes value after the uid address, wherein the first byte value is 0x64, and the second byte value is 0x0e, merged as 0x64e = 1614. the conversion result is as follows: #define set_iapen bit_tmp=ea;ea=0;ta=0xaa;ta=0x 55;chpcon|=set_bit0 ;ea=bit_tmp #define set_iapgo bit_tmp=ea;ea=0;ta=0xaa;ta=0x55;iaptrg|=set_bit0 ;ea=bit_tmp #define clr_iapen bit_tmp=ea;ea=0;ta=0xaa;ta=0 x 55;chpcon&=~set_bit0;ea=bit_tmp void read_bandgap() { uint8 bandgaphigh,bandgaplow; s et_iapen; // enable iapen iapal = 0x0c; iapah = 0x00; i apcn = 0x04; set_iapgo ; // trig set iapgo bandgaphigh = iapfd; iapal = 0x0d;
N76E003 datasheet jun 26 , 201 7 page 195 of 267 rev. 1.02 iapah = 0x00; iapcn = 0 x04; set_iapgo ; // trig set iapgo bandgaplow = iapfd; bandgaplow = bandgaplow&0x0f; c lr_iapen; // disable iapen bandgap_value = (bandgaphigh<<4)+bandgaplow; bandgap_voltage = 3072/(0x1000/bandgap_value); } band - gap as adc input to calculate the vdd va lue: N76E003 internal embedded band - gap voltage also can be the internal adc input. this input is useful to measure vref value then means can know the vdd value from adc convert result. for a more accuracy result when band - gap as adc input, always give up the first three times convert data in register after adc enable. doubl e bandgap_voltage,vdd_voltage ; void adc_bypass (void) // the first three times convert should be bypass { unsigned char ozc; for (ozc=0;ozc<0x03;ozc++) { clr_adcf; set_ad cs; while(adcf == 0); } } void main (void) { double bgvalue; read_bandgap(); enable_adc_bandgap; adc_bypass(); clr_adcf; set_adcs; while(adcf == 0); bgvalue = (adcrh<<4) + adcrl; vdd_voltage = (0xfff/bgvalue)*bandgap_voltage;
N76E003 datasheet jun 26 , 201 7 page 196 of 267 rev. 1.02 printf (" \ n bandgap voltage = %e", bandgap_voltage); printf (" \ n vdd voltage = %e", vdd_voltage); while(1); }
N76E003 datasheet jun 26 , 201 7 page 197 of 267 rev. 1.02 18.2 control registers of adc adccon0 C adc control 0 (bit - addressable) 7 6 5 4 3 2 1 0 adcf adcs e tg sel1 e tg sel0 adchs3 adchs2 adchs1 ad chs0 r/w r/w r/w r/w r/w r/w r/w r/w address: e 8h reset value: 0000 0000b bit name description 7 adcf adc flag this flag is set when an a/d conversion is completed. the adc result can be read. while this flag is 1, adc cannot start a new converting . thi s bit is cleared by software. 6 adcs a/d co nverting software start trigger setting this bit 1 triggers an a/d conversion. this bit remains logic 1 during a/d converting time and is automatically cleared via hardware right after conversion complete. the me aning of writing and reading adcs bit is different. writing: 0 = no effect. 1 = start an a/d converting. reading: 0 = adc is in idle state. 1 = adc is busy in converting. 5:4 e tg sel[1:0] external trigger so urce select when adcex (adccon 1 . 1 ) is set, th ese bits select which pin output triggers adc conversion. 00 = pwm0. 01 = pwm2. 10 = pwm4. 11 = stadc pin. 3 :0 adchs[ 3 :0] a/d converting channel select this filed select s the activating analog input source of adc. if adcen is 0, all inputs are disconnecte d. 0000 = ain0. 0001 = ain1. 0010 = ain2. 0011 = ain3. 0100 = ain4. 0101 = ain5. 0110 = ain6. 0111 = ain7 1 000 = internal band - gap voltag . others = reserved .
N76E003 datasheet jun 26 , 201 7 page 198 of 267 rev. 1.02 adccon1 C adc control 1 7 6 5 4 3 2 1 0 - stadcpx - - etgtyp[1:0] adcex adcen - r/w - - r/w r/ w r/w address: e1h reset value : 00 0 0 0000b bit name description 7 - reserved 6 stadcpx external start adc trigger pin select 0 = assign stadc to p0.4. 1 = assign stadc to p1.3. note that stadc will exchange immediately once setting or clearing this bit. 5 :4 - reserved 3:2 e tg typ[1:0] external trigger type select when adcex (adccon 1 . 1 ) is set, these bits select which condition triggers adc conversion. 00 = falling edge on pwm0/2/4 or stadc pin . 01 = rising edge on pwm0/2/4 or stadc pin . 10 = central poi nt of a pwm period. 11 = end point of a pwm period. note that the central point interrupt or the period point interrupt is only available for pwm center - aligned type. 1 adcex adc ext ernal conversion trigger select this bit select the methods of triggering an a/d conversion. 0 = a/d conversion is started only via setting adcs bit. 1 = a/d conversion is started via setting adcs bit or by external trigger source depending on e tg sel[1:0] and e tg typ[1:0]. note that while adcs is 1 (busy in converting), the adc will ignore the following external trigger until adcs is hardware cleared. 0 adcen adc enable 0 = adc circuit off . 1 = adc circuit on . adccon2 C adc control 2 7 6 5 4 3 2 1 0 adfben adcmpop adcmpen adcmpo - - - adcdly.8 r/w r/w r/w r - - - r/w address : e2h reset value : 0000 0000b bit name description 7 ad fb en adc compare result asserting fault brake enable 0 = adc asserting fault brake disabled . 1 = adc asserting fault brake enabled. fault brake is asserted once its compare result adcmpo is 1. meanwhi le, pwm channels output fault brake data. pwmrun (pwmcon0.7) will also be automatically cleared by hardware. the pwm output re sumes when pwmrun is set again. 6 adcmpop adc comparator output polarity 0 = adcmpo is 1 i f adcr[ 11 :0] is greater than or equal t o adcmp[ 11 :0 ]. 1 = adcmpo is 1 i f adcr[ 11 :0] is less than adcmp[ 11 :0 ].
N76E003 datasheet jun 26 , 201 7 page 199 of 267 rev. 1.02 bit name description 5 adcmpen adc result comparator enable 0 = adc result comparator disabled . 1 = adc result comparator enabled . 4 adcmpo adc comparator output value this bit is the output value of adc result compar ator based on the setting of acmpop. this bit updates after every a/d conversion complete. 3 :1 - reserved 0 adcdly.8 adc external trigger delay counter bit 8 see adcdly register. ain dids C adc channel digital input disconnect 7 6 5 4 3 2 1 0 p 11 dids p0 3 dids p0 4 dids p0 5 dids p0 6 dids p0 7 dids p 30 dids p 17 dids r/w r/w r/w r/w r/w r/w r/w r/w address: f6h reset value: 0000 0000b bit name description n ain n dids adc channel digital input disable 0 = adc channel n digital input e nabled. 1 = adc ch annel n digital input d isabled. adc channel n is read always 0. adcdly C adc trigger delay counter 7 6 5 4 3 2 1 0 adcdly[7:0] r/w address: e3h reset value: 0000 0000b bit name description 7:0 adcdly[7:0] adc external trigger delay counter low byte th is 8 - bit field combined with adccon2.0 forms a 9 - bit counter. this counter inserts a delay after detecting the external trigger. an a/d converting starts after this period of delay. external trigger delay time = . note that this field is valid only when adcex (adccon 1 . 1 ) is set. user should not modif y adcdly during pwm run time if selecting pwm output as the external adc trigger source. adc rh C adc result high byte 7 6 5 4 3 2 1 0 adcr[ 11 : 4 ] r address: c3 h reset value: 0000 0000b b it name description 7 :0 adcr[ 11 : 4 ] adc result high byte the most significant 8 bits of the adc result store d in this register. adc f adcdly
N76E003 datasheet jun 26 , 201 7 page 200 of 267 rev. 1.02 adcrl C adc result low byte 7 6 5 4 3 2 1 0 - - - - adcr[3:0] - - - - r address: c2h reset value: 0000 0000b bit name descri ption 3 :0 adcr[ 3 :0] adc result low byte the least significant 4 bits of the adc result store d in this register. adc mp h C adc compare high byte 7 6 5 4 3 2 1 0 adc mp [ 11 : 4 ] w/r address: c f h reset value: 0000 0000b bit name description 7:0 adc mp [ 11 : 4 ] a dc compare high byte the most significant 8 bits of the adc compare value store s in this register. adc mp l C adc compare low byte 7 6 5 4 3 2 1 0 - - - - adcmp[3:0] - - - - w/r address: c e h reset value: 0000 0000b bit name description 3 :0 adc mp [ 3 :0] ad c compare low byte the least significant 4 bits of the adc compare value store s in this register.
N76E003 datasheet jun 26 , 201 7 page 201 of 267 rev. 1.02 19. timed access protect ion (ta) the N76E003 has several features such as wdt and brown - out detection that are crucial to proper operation of the system. if lea ving these control registers unprotected, errant code may write undetermined value into them and results in incorrect operation and loss of control. to prevent this risk, the N76E003 has a protection scheme , which limits the write access to critical sfrs. this protection scheme is implemented using a timed access (ta). the following registers are related to the ta process . ta C timed access 7 6 5 4 3 2 1 0 ta[7:0] w address: c7h reset value : 0000 0000b bit name description 7:0 ta[7:0] timed access the t imed access register controls the access to protected sfrs. to access protected bits, user should first write aah to the ta and immediately followed by a write of 55h to ta. after these two steps, a writing permission window is opened for 4 clock cycles du ring this period that user may write to protected sfrs. in timed access method, the bits, which are protected, have a timed write enable window. a write is successful only if this window is active, otherwise the write will be discarded. when the software writes aah to ta, a counter is started. this counter waits for 3 clock cycles looking for a write of 55h to ta. if the second write of 55h occurs within 3 clock cycles of the first write of aah, then the timed access window is opened. it remains open for 4 clock cycles during which user may write to the protected bits. after 4 clock cycles, this window automatically closes. once the window closes, the procedure should be repeated to write another protected bits. not that the ta protected sfrs are required timed access for writing but reading is not protected. user may read ta protected sfr without giving aah and 55h to ta register. the suggestion code for opening the timed access window is shown below. ( clr ea ) ;if any interrupt is enabled, disable tempo rally mov ta,#0aah mov ta,#55h (instruction that writes a ta protected register) (setb ea) ;resume interrupts enabled any enabled interrupt should be disabled during this procedure to avoid delay between these three writings. if there is no interrup t enabled, the clr ea and setb ea instructions can be left out.
N76E003 datasheet jun 26 , 201 7 page 202 of 267 rev. 1.02 examples of timed assess are shown to illustrate correct or incorrect writing process. example 1, mov ta,#0aah ; 3 clock cycles mov ta,#55h ; 3 clock cycles orl wdcon ,#data ; 4 clock cycles example 2, mov ta,#0aah ; 3 clock cycles mov ta,#55h ; 3 clock cycles nop ;1 clock cycle anl bodcon0 ,#data ; 4 clock cycles example 3, mov ta,#0aah ; 3 clock cycles mov ta,#55h ; 3 clock cycles mov wdcon ,#data1 ; 3 clock cycles orl bodcon0 ,#d ata2 ; 4 clock cycles example 4, mov ta,#0aah ; 3 clock cycles nop ;1 clock cycle mov ta,#55h ; 3 clock cycles anl bodcon0 ,#data ; 4 clock cycles in the first example, the writing to the protected bits is done before the 3 - clock - cycle window closes . in example 2, however, the writing to bodcon0 does not complete during the window opening, there will be no change of the value of bodcon0 . in example 3, the wdcon is successful written but the bodcon0 write is out of the 3 - clock - cycle window. therefore , the bodcon0 value will not change either. in example 4, the second write 55h to ta completes after 3 clock cycles of the first write ta of aah, and thus the timed access window is not opened at all, and the write to the protected byte affects nothing.
N76E003 datasheet jun 26 , 201 7 page 203 of 267 rev. 1.02 20. int errupt system 20.1 interrupt overview the purpose of the interrupt is to make the software deal with unscheduled or asynchronous events. the N76E003 has a four - priority - level interrupt structure with 1 8 interrupt sources. each of the interrupt sources has an in dividual priority setting bits, interrupt vector and enable bit. in addition, the interrupts can be globally enabled or disabled. when an interrupt occurs, the cpu is expected to service the interrupt. this service is specified as an interrupt service rout ine (isr). the isr resides at a predetermined address as shown in table 20 - 1 . i nterrupt vectors . when the interrupt occurs if enabled, the cpu will vector to the respective location depending on interrupt source , e xecute the code at this location, stay in an interrupt service state until the isr is done . once an isr has begun, it can be interrupted only by a higher priority interrupt. the isr should be terminated by a return from interrupt instruction reti. this ins truction will force the cpu return to the instruction that would have been next when the interrupt occurred. table 20 - 1 . i nterrupt vectors source vector address vector number source vector address vector numbe r reset 0000h - spi interrupt 004bh 9 external i nterrupt 0 0003h 0 wdt interrupt 0053h 10 timer 0 o verflow 000bh 1 adc interrupt 00 5 bh 11 external i nterrupt 1 0013h 2 input capture interrupt 00 6 3h 12 timer 1 o verflow 001bh 3 pwm interrupt 00 6 bh 13 se rial p ort 0 interrupt 0023h 4 fault brake interrupt 00 7 3h 14 timer 2 event 002bh 5 serial port 1 interrupt 007bh 15 i 2 c status/timer - out interrupt 0033h 6 timer 3 overflow 0083h 16 pin interrupt 003bh 7 self w ake - u p t imer interrupt 008bh 17 brown - out d etection interrupt 0043h 8
N76E003 datasheet jun 26 , 201 7 page 204 of 267 rev. 1.02 20.2 enabling interrupts each of individual interrupt sources can be enabled or disabled through the use of an associated interrupt enable bit in the ie and eie sfrs. there is also a global enable bit ea bit (ie.7), which can be cleared to disable all the interrupts at once. it is set to enable all individually enabled interrupts. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt - enable settings. note that interrupts which occur w hen the ea bit is set to logic 0 will be held in a pending state, and will not be serviced until the ea bit is set back to logic 1. all interrupt flags that generate interrupts can also be set via software. thereby software initiated interrupts can be gene rated. note that every interrupts, if enabled, is generated by a setting as logic 1 of its interrupt flag no matter by hardware or software. user should take care of each interrupt flag in its own interrupt service routine (isr). most of interrupt flags sh ould be cleared by writing it as logic 0 via software to avoid recursive interrupt requests. ie C interrupt enable ( bit - addressable ) 7 6 5 4 3 2 1 0 ea e adc e bod es et1 ex1 et0 ex0 r/w r/w r/w r/w r/w r/w r/w r/w address: a8h reset value : 0000 0000b bit name description 7 ea enable all interrupt this bit globally enables/disables all interrupts that are individually enabled. 0 = a ll interrupt sources disable d . 1 = e ach interrupt enable d depending on its individual mask setting. individual interrupts wil l occur if enabled. 6 e adc enable adc interrupt 0 = adc interrupt disable d . 1 = interrupt generated by adcf ( adccon0.7 ) enable d . 5 ebod enable brown - out interrupt 0 = b rown - out detection interrupt disable d . 1 = interrupt generated by bof ( bodcon0 .3 ) enab le d . 4 es enable serial port 0 interrupt 0 = s erial port 0 interrupt disable d . 1 = interrupt generated by ti ( scon.1 ) or ri ( scon.0) enable d . 3 et1 enable timer 1 interrupt 0 = timer 1 interrupt disable d . 1 = interrupt generated by tf1 ( tcon.7 ) enable d . 2 ex1 enable external interrupt 1 0 = e xternal interrupt 1 disable d . 1 = interrupt generated by ? ? ? ? ? ? ? pin (p 1 . 7 ) enable d . 1 et0 enable timer 0 interrupt 0 = timer 0 interrupt disable d . 1 = interrupt generated by tf0 ( tcon.5 ) enable d .
N76E003 datasheet jun 26 , 201 7 page 205 of 267 rev. 1.02 bit name description 0 ex0 enable exter nal interrupt 0 0 = e xternal interrupt 0 disable d . 1 = interrupt generated by ? ? ? ? ? ? ? pin ( p 3 .0 ) enable d . e ie C extensive interrupt enable 7 6 5 4 3 2 1 0 e t2 e spi e fb ewdt e pwm e cap e pi e i2c r/w r/w r/w r/w r/w r/w r/w r/w address: 9b h reset value : 000 0 0000b bit name description 7 e t2 enable timer 2 interrupt 0 = timer 2 interrupt disable d . 1 = interrupt generated by tf2 (t2con.7) enable d . 6 e spi enable spi interrupt 0 = spi interrupt disable d . 1 = interrupt generated by spif (spsr.7), spiovf (spsr.5 ), or modf (spsr.4) enable . 5 e fb enable fault brake interrupt 0 = fault brake interrupt disable d . 1 = interrupt generated by fb f ( fb d.7) enable d . 4 ewdt enable wdt interrupt 0 = wdt interrupt disable d . 1 = interrupt generated by wdtf ( wdcon.5 ) enable d . 3 epwm enable pwm interrupt 0 = pwm interrupt disable d . 1 = interrupt generated by pwmf ( pwmcon0.5 ) enable d . 2 ecap enable input capture interrupt 0 = i nput capture interrupt disable d . 1 = interrupt generated by any flags of capf[2:0] ( capcon0[2:0] ) enab le d . 1 e pi enable pin interrupt 0 = p in interrupt disable d . 1 = interrupt generated by any flags in pif register enable d . 0 ei2c enable i 2 c interrupt 0 = i 2 c interrupt disable d . 1 = interrupt generated by si ( i2con.3 ) or i2tof ( i2toc.0) enable d . eie1 C extensive interrupt enable 1 7 6 5 4 3 2 1 0 - - - - - ewkt et3 es _ 1 - - - - - r/w r/w r/w address: 9 c h reset value: 0000 0000b bit name description 2 ewkt enable wkt interrupt 0 = wkt interrupt disable d . 1 = interrupt generated by wktf (wkcon.4) enabl e d .
N76E003 datasheet jun 26 , 201 7 page 206 of 267 rev. 1.02 bit name description 1 et3 enable timer 3 interrupt 0 = timer 3 interrupt disable d . 1 = interrupt generated by tf3 (t3con.4) enable d . 0 es_1 enable serial port 1 interrupt 0 = s erial port 1 interrupt disable d . 1 = interrupt generated by ti_1 ( scon_1.1 ) or ri_1 ( scon_1.0) enable d .
N76E003 datasheet jun 26 , 201 7 page 207 of 267 rev. 1.02 20.3 interrupt priorit ies there are four priority levels for all interrupts. they are level highest, high, low, and lowest ; and they are represented by level 3, level 2, level 1, and level 0 . the interrupt sources can be individually set to one of four priority levels by setting their own priority bits. table 20 - 2 . interrupt priority level setting lists four priority setting. naturally, a low level priority interrupt can itself be interrupted by a high level priority inter rupt, but not by any same level interrupt or lower level. in addition, there exists a pre - defined natural priority among the interrupts themselves. the natural priority comes into play when the interrupt controller has to resolve simultaneous requests havi ng the same priority level. in case of multiple interrupts, the following rules apply: 1. while a low priority interrupt handler is running, if a high priority interrupt arrives, the handler will be interrupted and the high priority handler will run. when the high priority handler does e , the low priority handler will resume. when this handler does e , control is passed back to the main program. 2. if a high priority interrupt is running, it cannot be interrupted by any other source C even if it is a high priority interrupt which is higher in natural priority. 3. a low - priority interrupt handler will be invoked only if no other interrupt is already executing. again, the low priority interrupt cannot preempt another low priority interrupt, even if th e later one is higher in natural priority. 4. if two interrupts occur at the same time, the interrupt with higher priority will execute first. if both interrupts are of the same priority, the interrupt which is higher in natural priority will be executed f irst. this is the only context in which the natural priority matters. this natural priority is defined as shown on table 20 - 3 . characteristics of each interrupt source . it also summarizes the interrupt sources, flag bits, vector a ddresses, enable bits, priority bits, natural priority and the permission to wake up the cpu from power - down mode. for details of waking cpu up from power - down mode, please see section 22.1 power - d own mode on page 226 .
N76E003 datasheet jun 26 , 201 7 page 208 of 267 rev. 1.02 table 20 - 2 . interrupt priority level setting interrupt priority control bits interrupt priority level iph / eiph / eiph1 ip / eip / eip2 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest) table 20 - 3 . characteristics of each interrupt source interrupt source vector a ddress interrupt flag (s) enable b it natural p riority priority c ontrol b its power - down wake - up reset 0000h - always enabled highest - yes external i nterrupt 0 0003h ie0 [1] ex0 1 px0, px0h yes brown - out 00 4 3h bof ( bodcon0 .3 ) ebod 2 pbod, pbodh yes watchdog t imer 00 53 h wdtf ( wdcon .5) e w dt 3 p w dt, p w dth yes timer 0 000bh tf0 [2] et0 4 pt0, pt0h no i 2 c status/time - out 0033h si + i2tof (i2toc.0) ei2c 5 pi2c, pi2ch no adc 005bh adcf eadc 6 padc, padch no external i nterrupt 1 0013h ie1 [1] ex1 7 px1, px1h yes pin interrupt 00 3 b h pif0 to pif7 (pif) [ 3 ] e pi 8 ppi, ppih yes timer 1 001bh tf1 [2] et1 9 pt1, pt1h no serial p ort 0 0023h ri + ti es 10 ps, psh no fault brake event 0073h fbf (fbd.7) efb 11 pfb, pfbh no spi 004bh spif (spsr.7) + modf (spsr.4) + spiovf (spsr.5) espi 12 pspi, pspih no timer 2 002bh tf2 [2] et2 13 pt2, pt2h no input capture 0063h capf[2:0] (capcon0[2:0]) ecap 14 pcap, pcaph no pwm interrupt 006bh pwmf epwm 15 ppwm, ppwmh no serial port 1 007bh ri_1 + ti_1 es_1 16 ps_1, psh_1 no timer 3 0083h tf3 [2] ( t3con.4 ) et3 17 pt3, pt3h no self wake - up timer 008bh wktf (wkcon.4) ewkt 18 pwkt, pwkth yes [1] while the external interrupt pin is set as edge triggered (i t x = 1), its own fla g i e x will be automatically cleared if the interrupt service routine (isr) is executed. while as level triggered (i t x = 0) , i e x follows the inverse of respective pin state. it is not controlled via software. [2] tf0 , tf1 , or tf3 is automatically cleared if the interrupt service routine (isr) is executed. on the contrary, be aware that tf2 is not. [ 3 ] if level triggered is selected for pin interrupt channel n , p ifn flag reflects the respective channel state. it is not controlled via software.
N76E003 datasheet jun 26 , 201 7 page 209 of 267 rev. 1.02 ip C interrupt priority (bit - addressable) [1] 7 6 5 4 3 2 1 0 - padc pbod ps pt1 px1 pt0 px0 - r/w r/w r/w r/w r/w r/w r/w address: b8h reset value: 0000 0000b bit name description 6 padc adc interrupt priority low bit 5 pbod brown - out detection interrupt priority low bit 4 ps serial port 0 interrupt priority low bit 3 pt1 timer 1 interrupt priority low bit 2 px1 external interru pt 1 priority low bit 1 pt0 timer 0 interrupt priority low bit 0 px0 external interrupt 0 priority low bit [1] ip is used in combination with the iph to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. iph C interrupt priority high [2] 7 6 5 4 3 2 1 0 - padch pbodh psh pt1h px1h pt0h px0h - r/w r/w r/w r/w r/w r/w r/w address: b7h , page0 reset value: 0000 0000b bit na me description 6 padc adc interrupt priority high bit 5 pbod brown - out detection interrupt priority high bit 4 psh serial port 0 interrupt priority high bit 3 pt1h timer 1 interrupt priority high bit 2 px1h external interrupt 1 priority high bit 1 pt 0h timer 0 interrupt priority high bit 0 px0h external interrupt 0 priority high bit [2] iph is used in combination with the ip respectively to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. eip C extensive interrupt priority [3] 7 6 5 4 3 2 1 0 pt2 pspi pfb pwdt ppwm pcap ppi pi2c r/w r/w r/w r/w r/w r/w r/w r/w address: efh reset value: 0000 0000b bit name descript ion 7 pt2 timer 2 interrupt priority low bit 6 pspi spi interrupt priority low bit 5 pfb fault brake interrupt priority low bit
N76E003 datasheet jun 26 , 201 7 page 210 of 267 rev. 1.02 bit name descript ion 4 pwdt wdt interrupt priority low bit 3 ppwm pwm interrupt priority low bit 2 pcap input capture interrupt priority low bi t 1 ppi pin interrupt priority low bit 0 pi2c i 2 c interrupt priority low bit [3] eip is used in combination with the eiph to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. eiph C extensive interrupt priority high [4] 7 6 5 4 3 2 1 0 pt2h pspih pfbh pwdth ppwmh pcaph ppih pi2ch r/w r/w r/w r/w r/w r/w r/w r/w address: f7h reset value: 0000 0000b bit name description 7 pt2h timer 2 interrupt priority high bit 6 pspih spi interrupt priority high bit 5 pfbh fault brake interrupt priority high bit 4 pwdth wdt interrupt priority high bit 3 ppwmh pwm interrupt priority high bit 2 pcaph input capture interrupt priority high bit 1 ppih pin interrupt priority high bit 0 pi2ch i 2 c interrupt priority high bit [4] eiph is used in combination with the eip to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. eip1 C extensive interrupt priority 1 [ 5 ] 7 6 5 4 3 2 1 0 - - - - - pwkt pt3 ps _ 1 - - - - - r/w r/w r/w address: feh, page: 0 reset value: 0000 0000b bit name description 2 pwkt wkt i nterrupt priority low bit 1 pt3 timer 3 interrupt priority low bit 0 ps _ 1 serial port 1 interrupt priority low bit [5] eip1 is used in combination with the eiph1 to determine the priority of each interrupt source. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration.
N76E003 datasheet jun 26 , 201 7 page 211 of 267 rev. 1.02 eiph1 C extensive interrupt priority high 1 [ 6 ] 7 6 5 4 3 2 1 0 - - - - - pwkth pt3h psh _ 1 - - - - - r/w r/w r/w address: ffh, page: 0 reset value: 0000 000 0b bit name description 2 pwkth wkt interrupt priority high bit 1 pt3h timer 3 interrupt priority high bit 0 psh _ 1 serial port 1 interrupt priority high bit [6] eiph1 is used in combination with the eip1 to determine the priority of each interrupt sour ce. see table 20 - 2 . interrupt priority level setting for correct interrupt priority configuration. 20.4 interrupt service the interrupt flags are sampled every system clock cycle. in the same cycle, the sampled interrup ts are polled and their priority is resolved. if certain conditions are met then the hardware will execute an internally generated lcall instruction , which will vector the process to the appropriate interrupt vector address. the conditions for generating t he lcall are, 1. an interrupt of equal or higher priority is not currently being serviced. 2. the current polling cycle is the last cycle of the instruction currently being executed. 3. the current instruction does n ot involve a write to any enabling or pr iority setting bits and is not a reti. if any of these conditions are not met, then the lcall will not be generated. the polling cycle is repeated every system clock cycle. if an interrupt flag is active in one cycle but not responded to for the above cond itions are not met, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. this means that the interrupt flag , which was once active but not serviced is not remembered. every polling cycle is new. the processor responds to a valid interrupt by executing an lcall instruction to the appropriate service routine. this action may or may not clear the flag, which caused the interrupt according to different interrupt source. the hardware lcall behaves exa ctly like the software lcall instruction. this instruction saves the program counter contents onto the stack ram but does not save the program status word (psw). the pc is reloaded with the vector address of that interrupt , which caused the lcall. executio n continues from the vectored address until an reti instruction is executed. on execution of the reti instruction, the processor pops the stack and loads the pc with the contents at the top of the stack. user should take care that the status of the stack. the processor does not notice anything if the stack contents are modified and will proceed with execution from the
N76E003 datasheet jun 26 , 201 7 page 212 of 267 rev. 1.02 address put back into pc. note that a simple ret instruction would perform exactly the same process as a reti instruction, but it would not i nform the interrupt controller that the interrupt service routine is completed. ret would leave the controller still thinking that the service routine is underway, making future interrupts impossible. 20.5 interrupt latency the response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. each interrupt flags are polled and priority decoded each system clock cycle. if a request is active and all three previous conditions are met, then the ha rdware generated lcall is executed. this lcall itself takes 4 clock cycles to be completed. thus, there is a minimum reaction time of 5 clock cycles between the interrupt flag being set and the interrupt service routine being executed. a longer response ti me should be anticipated if any of the three conditions are not met. if a higher or equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the service routine currently being executed. if the polling cycle is n ot the last clock cycle of the instruction being executed, then an additional delay is introduced. the maximum response time (if no other interrupt is currently being service d or the new interrupt is of greater priority ) occurs if the device is performing a reti , and then executes a longest 6 - clock - cycle instruction as the next instruction. from the time an interrupt source is activated (not detected), the longest reaction time is 1 6 clock cycles. this period includes 5 clock cycles to complete reti , 6 cloc k cycles to complete the longest instruction , 1 clock cycle to detect the interrupt, and 4 clock cycles to complete the hardware lcall to the interrupt vector location. thus in a single - interrupt system the interrupt response time will always be more than 5 clock cycles and not more than 1 6 clock cycles. 20.6 external interrupt pins the external interrupt ? ? ? ? ? ? ? and ? ? ? ? ? ? ? can be used as interrupt sources. they are selectable to be either edge or level triggered depending on bits it0 (tcon.0) and it1 (tcon.2). t he bits ie0 (tcon.1) and ie1 (tcon.3) are the flags those are checked to generate the interrupt. in the edge triggered mode, the ? ? ? ? ? ? ? or ? ? ? ? ? ? ? inputs are sampled every system clock cycle . if the sample is high in one cycle and low in the next, then a hi gh to low transition is detected and the interrupts request flag ie0 or ie1 will be set. since the external interrupts are sampled every system clock, they have to be held high or low for at least one system clock cycle. the ie0 and ie1 are automatically c leared when the interrupt service routine is called. if the level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is serviced. the ie0 and ie1 will not be cleared by the
N76E003 datasheet jun 26 , 201 7 page 213 of 267 rev. 1.02 hardware on entering the service rou tine. in the level triggered mode, ie0 and ie1 follows the inverse value of ? ? ? ? ? ? ? and ? ? ? ? ? ? ? pins. if interrupt pins continue to be held low even after the service routine is completed, the processor will acknowledge another interrupt request from the sam e source. both ? ? ? ? ? ? ? and ? ? ? ? ? ? ? can wake up the device from the power - down mode. tcon C timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r (level) r/w (edge) r/w r (level) r/w (edge) r/w address: 8 8h reset value: 0000 0000b bit name description 3 ie1 external interrupt 1 edge flag if it1 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. it remain set until cleared via software or cleared by hardware in t he beginning of its interrupt service routine. if it1 = 0 (low level trigger), this flag follows the inverse of the ? ? ? ? ? ? ? input sig n als logic level. software cannot control it. 2 it1 external interrupt 1 type select this bit selects by which type that ? ? ? ? ? ? ? is triggered. 0 = ? ? ? ? ? ? ? is low level triggered. 1 = ? ? ? ? ? ? ? is falling edge triggered. 1 ie0 external interrupt 0 edge flag if it0 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. it remain set until cle ared via software or cleared by hardware in the beginning of its interrupt service routine. if it0 = 0 (low level trigger), this flag follows the inverse of the ? ? ? ? ? ? ? input sig n als logic level. software cannot control it. 0 it0 external interrupt 0 type select this bit selects by which type that ? ? ? ? ? ? ? is triggered. 0 = ? ? ? ? ? ? ? is low level triggered. 1 = ? ? ? ? ? ? ? is falling edge triggered.
N76E003 datasheet jun 26 , 201 7 page 214 of 267 rev. 1.02 21. in - application - programming (iap) unlike a s real - time operation, to update flash data often takes long time. furthe rmore, it is a quite complex timing procedure to erase, program, or read flash data. the N76E003 carried out the flash operation with convenient mechanism to help user re - programming the flash content by in - application - programming (iap). iap is an in - circu it electrical erasure and programming method through software. after iap enabl ing by setting iap en (chpcon.0 with ta protected) and set ting the enable bit in iapuen that allows the target block to be updated , user can easily fill the 16 - bit target address in iap ah and iap al, data in iap fd , and command in iap cn. then the iap is ready to begin by setting a triggering bit iap go ( iap trg.0). note that iap trg is also ta protected. at this moment, the cpu holds the program counter and the built - in iap automation t akes over to control the internal charge - pump for high voltage and the detail signal timing. the erase and program time is internally controlled disregard of the operating voltage and frequency. nominally, a page - erase time is 5 ms and a byte - program time is 23.5 s. after iap action completed, the program counter continues to run the following instructions. the iap go bit will be automatically cleared. an iap failure flag, iapff (chpcon.6), can be check whether the previous iap operation was successful or n ot. through this progress, user can easily erase, program, and verify the flash memory by just taking care of pure software. the following registers are relate d to iap processing. config2 7 6 5 4 3 2 1 0 cboden - cbov[1 :0] boiap cborst - - r/w - r/w r/w r/w - - factory default value: 1111 1111b bit name description 3 boiap brown - out inhibiting iap this bit decide whether iap erasing or programming is inhibited by brown - out status. this bit is valid only when brown - out detection is enabled. 1 = iap eras ing or programming is inhibited if v dd is lower than v bod . 0 = iap erasing or programming is allowed under any workable v dd . chpcon C chip control ( ta protected ) 7 6 5 4 3 2 1 0 swrst iapff - - - - bs i a pen w r/w - - - - r/w r/w address: 9fh reset valu e : see table 6 - 2 . sfr definitions and reset values bit name description 6 iapff i a p fault flag
N76E003 datasheet jun 26 , 201 7 page 215 of 267 rev. 1.02 bit name description the hardware will set this bit after iapgo (isptrg.0) is set if any of the following condition is met: ( 1 ) the accessi ng address is oversize . ( 2 ) iap cn command is invalid. ( 3 ) iap erases or programs updating un - enabled block. ( 4 ) iap erasing or programming operates under v bod while boi a p (config2.5) remains un - program med 1 with boden ( bodcon0 .7) as 1 and borst ( bodcon0 . 2 ) as 0. this bit should be cleared via software. 0 i a pen i a p enable 0 = iap function disable d . 1 = iap function enable d . once enabl ing i a p function , the hirc will be turned on for timing control. to clear i a pen should always be the last instruction after i a p operation to stop internal oscillator if reducing power consumption is concerned . iapuen C iap updating enable ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - cfuen lduen apuen - - - - - r/w r/w r/w address: a5 h reset value: 0000 0000b bit name description 2 cfuen config bytes updated enable 0 = inhibit erasing or programming config bytes by iap. 1 = allow erasing or programming config bytes by iap. 1 lduen ldrom updated enable 0 = inhibit erasing or programming ldrom by iap. 1 = allow erasing or programm ing ldrom by iap. 0 apuen aprom updated enable 0 = inhibit erasing or programming aprom by iap. 1 = allow erasing or programming aprom by iap. i a pcn C i a p control 7 6 5 4 3 2 1 0 i a p b [ 1 : 0 ] foen fcen fctrl[3:0] r/w r/w r/w r/w address: afh reset value : 00 11 0000b bit name description 7:6 i a p b [ 1 : 0 ] i a p control this byte is used for i a p command. for details, see table 21 - 1 . iap modes and command codes . 5 foen 4 fcen 3:0 fctrl[3:0]
N76E003 datasheet jun 26 , 201 7 page 216 of 267 rev. 1.02 iap ah C iap address high byte 7 6 5 4 3 2 1 0 iap a[15:8] r/w address: a7h reset value : 0000 0000b bit name description 7:0 iap a[15:8] iap address high byte iap ah contains address iap a[15:8] for iap operations. iap al C iap address low byte 7 6 5 4 3 2 1 0 iap a[7:0] r/w addr ess: a6h reset value : 0000 0000b bit name description 7:0 iap a[7:0] iap address low byte iap al contains address iap a[7:0] for iap operations. iap fd C iap flash data 7 6 5 4 3 2 1 0 iap fd[7:0] r/w address: aeh reset value : 0000 0000b bit name descripti on 7:0 iap fd[7:0] iap flash data this byte contains flash data , which is read from or is going to be written to the flash m emory. user should write data into iap fd for program mode before triggering iap processing and read data from iap fd for read/verify mode after iap processing is finished.
N76E003 datasheet jun 26 , 201 7 page 217 of 267 rev. 1.02 i a ptrg C i a p trigger ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - i a pgo - - - - - - - w address: a4h reset value : 0000 0000b bit name description 0 iapgo i a p go iap begins by setting this bit as logic 1. after th is instruction, the cpu holds the program counter (pc) and the iap hardware automation takes over to control the progress. after iap action completed, the program counter continues to run the following instruction. the iapgo bit will be automatically clear ed and always read as logic 0. before triggering an iap action, interrupts (if enabled) should be temporary disabled for hardware limitation. the program process should follows below . clr ea mov ta,#0aah mov ta,#55h orl iaptrg,#01h (setb ea) 21.1 iap com mands the N76E003 provides a wide range of application s to perform i a p to aprom, ldrom , or config bytes. the i a p action mode and the destination of the flash block are defined by i a p control register iap cn. table 21 - 1 . iap modes and command codes iap mode iap cn iap a[15:0] { iap ah, iap al } iap fd[7:0] iap b [ 1 : 0 ] foen fcen fctrl[3:0] company id r ead xx [1] 0 0 1011 x dah device id r ead x x 0 0 1100 low - byte did: 0000h high - byte did: 0001h low - byte did: 50h high - b yte did: 36 h 96 - bit unique code r ead x x 0 0 0100 0000h to 000bh data out aprom p age - e rase 0 0 1 0 0010 address in [ 2 ] ffh ldrom p age - e rase 0 1 1 0 0010 address in [ 2 ] ffh aprom byte - program 0 0 1 0 0001 address in data in ldrom byte - program 0 1 1 0 0001 add ress in data in aprom byte - r ead 0 0 0 0 0000 address in data out ldrom byte - r ead 0 1 0 0 0000 address in data out all config bytes e rase 1 1 1 0 0010 0000h ffh
N76E003 datasheet jun 26 , 201 7 page 218 of 267 rev. 1.02 iap mode iap cn iap a[15:0] { iap ah, iap al } iap fd[7:0] iap b [ 1 : 0 ] foen fcen fctrl[3:0] config byte - p rogram 1 1 1 0 0001 config0: 0000h config1: 0001h config2: 0002h config4: 0004h dat a in config byte - r ead 1 1 0 0 0000 config0: 0000h config1: 0001h config2: 0002h config4: 0004h data out [1] x means dont care. [2] each page is 128 byte s size. therefore, the address should be the address pointed to the target page. 21.2 i a p user guide i a p facilitates the updating flash contents in a convenient way; however, user should follow some restricted laws in order that the i a p operates correctly. without noticing warnings will possible cause undetermined results even serious damages of devices. fu rthermore, this paragraph will also support useful suggestions during i a p procedures. (1) if no more i a p operation is need ed , user should clear i a pen (chpcon.0). it will make the system void to trigger iap unaware. furthermore, i a p requires the hirc runnin g. if the external clock source is selected , disabling iap will stop the hirc for saving power consumption. note that a write to i a pen is ta protected. ( 2 ) when the lock bit (config0.1) is activated, i a p reading, writing, or erasing can still be valid. dur ing iap progress, interrupts (if enabled) should be disabled temporally by clearing ea bit for implement limitation. do not attempt to erase or program to a page that the code is currently executing . this will cause unpredictable program behavior and may c orrupt program data. 21.3 using flash memory as data storage in general application, there is a need of d ata storage , which is non - volatile so that it remains its content even after the power is off. therefore, in general application user can read back or updat e the data, which rules as parameters or constants for system control . the flash memory array of the N76E003 supports iap function and a ny byte in the flash memory array may be read using the movc instruction and thus is suitable for use as non - volatile da ta storage. iap provides erase and program function that makes it easy for one or more bytes within a page to be erased and programmed in a routine . iap performs in the application under the control of the microcontrollers firmware . be aware of flash memo ry writing endurance of 100,000 cycles. a demo is illustrated as follows.
N76E003 datasheet jun 26 , 201 7 page 219 of 267 rev. 1.02 assembly demo code: ;******************************************************************** ********** ; this code illustrates how to use iap to make aprom 201h as a byte of ; data flas h when user code is executed in aprom. ;******************************************************************** ********** page_erase_ap equ 00100010b byte_program_ap equ 00100001b org 0000h mov ta, # 0a a h ;chpcon is ta protected mov ta,#55h orl chp con,#00000001b ;iapen = 1, enable iap mode mov ta, # 0a a h ; iapuen is ta protected mov ta,#55h orl iapuen ,#00000001b ;ap u en = 1, enable aprom update mov iapcn,# page_erase_ap ; erase page 200h~27fh mov iapah,# 02 h mov iapal,#00h mov iapfd,#0ffh mov ta, # 0a a h ;iaptrg is ta protected mov ta,#55h orl iaptrg,#00000001b ;write 1 to iapgo to trigger iap process mov iapcn,# byte_program_ap ;program 201h with 55h mov iapah,#02h mov iapal,#01h mov iapfd,#55h mov ta, # 0a a h mov ta,#55h orl iaptrg,#0 0000001b mov ta, # 0a a h mov ta,#55h an l iapuen ,# 11111110 b ;ap u en = 0 , disable aprom update mov ta, # 0a a h mov ta,#55h an l chpcon,# 11111110 b ;iapen = 0 , disable iap mode mov dptr,#201h clr a movc a,@a+dptr ;read content of address 201h mov p0,a sjmp $
N76E003 datasheet jun 26 , 201 7 page 220 of 267 rev. 1.02 c language demo code: // ******************************************************************** ********** // this code illustrates how to use iap to make aprom 201h as a byte of // data flash when user code is executed in aprom. // **************** **************************************************** ********** #define page_erase_ap 0x22 #define byte_program_ap 0x21 /*data flash, as part of aprom, is read by movc. data flash can be defined as 128 - element array in code area from absolute address 0x 0200 */ volatile unsigned char code data_flash[128] _at_ 0x0200; main (void) { ta = 0 xaa; // chpcon is ta protected ta = 0x55; chpcon |= 0x01; // iapen = 1, enable iap mode ta = 0 xaa; //iapuen is ta protected ta = 0x55; iapuen |= 0x01; // ap u en = 1, enable aprom update iapcn = page_erase_ap ; //erase page 200h~27fh iapah = 0x02; iapal = 0x0 0 ; iapfd = 0 x ff ; ta = 0 xaa; // iaptrg is ta protected ta = 0x55; iaptrg |= 0x01; // write 1 to iapgo to trigger iap process iapcn = byte_program_ap ; // program 201h with 55h iapah = 0x02; iapal = 0x0 1 ; iapfd = 0x 55 ; ta = 0 xaa; ta = 0x55; iaptrg |= 0x01; // write 1 to iapgo to trigger iap process ta = 0 xaa; //iapuen is ta protected ta = 0x55; iapuen &= ~0x01; // ap u en = 0 , dis able aprom update ta = 0 xaa; //chpcon is ta protected ta = 0x55; chpcon &= ~0x01; // iapen = 0 , disable iap mode p0 = data_flash [1]; //read content of address 200h+1 while(1); } 21.4 in - system - programming (isp) the flash memory supports both hardware programming and in - application - programming (iap). i f the product is just under development or the end product needs firmware updating in the hand of an end user, the hardware programming mode will make repeated programming difficult and inconvenient. in -
N76E003 datasheet jun 26 , 201 7 page 221 of 267 rev. 1.02 system - programming (isp) makes it easy and possible. isp performs flash memory updating without removing the microcontroller from the system. it allows a device to be re - programmed under software control. furthermore, the capability to update the application firmware makes wide range of applications possible. u ser can develop a custom boot code that reside s in ldrom . the maximum size of ldrom i s 4k bytes. user developed boot code can be re - programmed by parallel writer or in - circuit - pro gramming (icp) too l. general speaking, an isp is carried out by a communication between pc and mcu. pc transfers the new user code to mcu through serial port. then boot code receives it and re - programs into user code through iap commands. nuvoton provides isp firmware and pc application for N76E003 . it makes user quite easy perform isp through uart port. please visit nuvoton 8 - bit microcontroller website: nuvoton 80c51 microcontroller technical support . a simple isp demo code is given below. assembly demo code: ;******************************************************************** ********** ; this code illustrates how to do aprom and conf ig iap from ldrom. ; aprom are re - programmed by the code to output p1 as 55h and p 0 a s a a h. ; the config 2 is also updated to disable bod reset . ; user needs to configure config0 = 0x7f, config1 = 0 xfe, config2 = 0 xff. ;************************************* ******************************* ********** page_erase_ap equ 00100010b byte_program_ap equ 00100001b byte_read_ap equ 00000000 b all_erase_config equ 11100010b byte_program_config equ 11100001b byte_read_config equ 11000000b org 0000h clr e a ;disable all interrupts call enable_ iap call enable_ap_update call erase_ap ; e rase ap data call program_ap ; p rogramming ap data call disable_ap_update call program_ap_verify ; v erify programmed ap data call read_ config ; r ead back config 2 call enable_config_update call erase_ config ; e rase config bytes call program_ config ; p rogramming config 2 with new data call disable_config_update call program_ config _verify ; v erify programmed config 2 call disable_ iap mov ta, # 0a a h ;ta protect ion mov ta,#55h ; anl chpcon,# 11111101b ;bs = 0, reset to aprom mov ta, # 0a a h
N76E003 datasheet jun 26 , 201 7 page 222 of 267 rev. 1.02 mov ta,#55h orl chpcon,#80h ; s oftware reset and reboot from aprom sjmp $ ;******************************************************************** ; iap subroutine ;******************************************************************** enable_ iap : mov ta, # 0a a h ;chpcon is ta protected mov ta,#55h orl chpcon,#00000001b ; iap en = 1, enable iap mode ret disable_ iap : mov ta, # 0a a h mov ta,#55h anl chpcon,#11111110b ; iap en = 0, disable iap mode ret enable_ ap_update : mov ta, # 0a a h ; iapuen is ta protected mov ta,#55h orl iapuen ,#00000001b ;ap u en = 1, enable aprom update ret disable_ ap_update : mov ta, # 0a a h mov ta,#55h an l iapuen ,# 11111110 b ;ap u en = 0 , disa ble aprom update ret enable_ config_update : mov ta, # 0a a h mov ta,#55h orl iapuen ,#00000 1 0 0 b ; cfu en = 1, enable config update ret disable_ config_update : mov ta, # 0a a h mov ta,#55h an l iapuen ,# 11111011 b ; cfu en = 0 , disable config update ret trigger _ iap : mov ta, # 0a a h ;iaptrg is ta protected mov ta,#55h orl iap trg,#00000001b ;write 1 to iap go to trigger iap process ret ;******************************************************************** ; iap ap rom function ;******************************* ************************************* erase_ap: mov iap cn,#page_erase_ap mov iapfd,#0ffh mov r0,#00h erase_ap_loop: mov iap ah,r0 mov iapal,#00h call trigger_ iap mov iapal,# 8 0h
N76E003 datasheet jun 26 , 201 7 page 223 of 267 rev. 1.02 call trigger_iap inc r0 cjne r0,# 4 4 h ,erase_ap_loop ret program_ap: mov iap cn,#byte_program_ap mov iap ah,#00h mov iap al,#00h mov dptr,#ap_code program_ap_loop: clr a movc a,@a+dptr mov iap fd,a call trigger_ iap inc dptr inc iap al mov a, iap al cjne a,# 14 ,program_ap_loop ret program_ap_verify: mov iap cn,#byte_rea d_ap mov iap ah,#00h mov iap al,#00h mov dptr,#ap_code program_ap_verify_loop: call trigger_ iap clr a movc a,@a+dptr mov b,a mov a, iap fd cjne a,b,program_ap_verify_error inc dptr inc iap al mov a, iap al cjne a,# 14 ,program_ap_verify_loop ret prog ram_ap_verify_error: call disable_ iap mov p0,#00h sjmp $ ;******************************************************************** ; iap config function ;******************************************************************** erase_ config : mov iap cn,#all_e rase_config mov iap ah,#00h mov iapa l ,#00h mov iap fd ,#0 ff h call trigger_ iap ret read_ config : mov iap cn,#byte_read_config mov iap ah,#00h mov iap al,# 02 h call trigger_ iap mov r7 , iap fd ret
N76E003 datasheet jun 26 , 201 7 page 224 of 267 rev. 1.02 program_ config : mov iap cn,#byte_program_config mov iap ah, #00h mov iap al,#0 2 h mov a,r7 anl a,#1 1 111 0 11b mov iap fd,a ; disable bod reset mov r 6 ,a ;temp data call trigger_ iap ret program_ config _verify: mov iap cn,#byte_read_config mov iap ah,#00h mov iap al,#0 2 h call trigger_ iap mov b,r 6 mov a, iap fd cjne a,b,program_config_verify_error ret program_config_verify_error: call disable_ iap mov p0,#00h sjmp $ ;******************************************************************** ; aprom code ;********************************************************** ********** ap_code: db 75h,0b1h, 00h ;opcode s of mov p 0m1 ,# 0 db 75h , 0 b3 h, 00h ;opcode s of mov p 1 m1 ,# 0 db 75h, 90h, 55h ;opcode s of mov p1,#55h db 75h, 0 8 0h , 0a a h ;opcode s of mov p 0 , # 0 a a h db 80h , 0f e h ;opcode s of sjmp $ end
N76E003 datasheet jun 26 , 201 7 page 225 of 267 rev. 1.02 22. power management the N76E003 has several features that help user to control the power consumption of the device. the power reduced feature has two option modes: idle mode and power - down mode, to save the power consumption. for a stable current consump tion, the state and mode of each pin should be taken care of. the minimum power consumption can be attaine d by giving the pin state just the same as the external pulls for example output 1 if pull - high is used or output 0 if pull - low. if the i/o pin is flo ating, user is recommended to leave it as quasi - bidirectional mode. if p2.0 is configured as a input - only pin, it should have a n external pull - up or pull - low, or enable its internal pull - up by setting p 20 up (p 2s . 7 ). pcon C power control 7 6 5 4 3 2 1 0 sm od smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value : see table 6 - 2 . sfr definitions and reset values bit name description 1 pd power - down mode setting this bit puts cpu into powe r - down mode. under this mode, both cpu and peripheral clocks stop and program counter (pc) suspends. it provides the lowest power consumption. after cpu is woken up from power - down , this bit will be automatically cleared via hardware and the program contin ue executing the interrupt service routine (isr) of the very interrupt source that woke the system up before. after return from the isr, the device continues execution at the instruction , which follows the instruction that put the system into power - down mo de. note that if idl bit and pd bit are set simultaneously, cpu will enter power - down mode. then it does not go to idle mode after exiting power - down . 0 idl idle mode setting this bit puts cpu into idle mode. under this mode, the cpu clock stops and progr am counter (pc) suspends but all peripherals keep activated . after cpu is woken up from idle, this bit will be automatically cleared via hardware and the program continue executing the isr of the very interrupt source that woke the system up before. after return from the isr, the device continues execution at the instruction which follows the instruction that put the system into idle mode. idle mode idle mode suspends cpu processing by holding the program counter. no program code are fetched and run in idl e mode. it forces the cpu state to be frozen. the program counter (pc), stack pointer (sp), program status word (psw), accumulator (acc), and the other registers hold their contents during idle mode. the port pins hold the logical states they had at the ti me idle was activated. generally, it saves considerable power of typical half of the full operating power. since the clock provided for peripheral function logic circuit like timer or serial port still remain in idle mode, the cpu can be released from the idle mode with any of enabled interrupt sources. user can put the device into idle mode by writing 1 to the bit idl (pcon.0). the instruction that sets the idl bit is the last instruction that will be executed before the device enters idle mode.
N76E003 datasheet jun 26 , 201 7 page 226 of 267 rev. 1.02 the idle m ode can be terminated in two ways. first, as mentioned, any enabled interrupt will cause an exit. it will automatically clear the idl bit, terminate idle mode, and the interrupt service routine (isr) will be executed. after using the reti instruction to ju mp out of the isr, execution of the program will be the one following the instruction , which put the cpu into idle mode. the second way to terminate idle mode is with any reset other than software reset. remember that if watchdog reset is used to exit idle mode, the widpd ( wdcon .4) needs to be set 1 to let wdt keep running in idle mode. 22.1 power - d own mode power - down mode is the lowest power state that the N76E003 can enter. it remain the power consumption as a a level by stopping the system clock source. bo th of cpu and peripheral functions like timers or uart are frozen. flash memory is put into its stop mode . all activity is completely stopped and the power consumption is reduced to the lowest possible value. the device can be put into power - down mode by w riting 1 to bit pd (pcon.1). the instruction that does this action will be the last instruction to be executed before the device enters power - down mode. in the power - down mode, ram maintains its content. the port pins output the values held by their own st ate before power - down respectively. there are several ways to exit the N76E003 from the power - down mode. the first is with all resets except software reset. brown - out reset will also wake up cpu from power - down mode. be sure that brown - out detection is ena bled before the system enters power - down . however, for least power consumption, it is recommended to enable low power bod in power - down mode. of course the external pin reset and power - on reset will remove the power - down status. after the external reset or power - on reset. the cpu is initialized and start executing program code from the beginning. the second way to wake the N76E003 up from the power - down mode is by an enabled external interrupt. the trigger on the external pin will asynchronously restart the system clock. after oscillator is stable, the device executes the interrupt service routine (isr) for the corresponding external interrupt. after the isr is completed, the program execution returns to the instruction after the one , which put s the device i nto power - down mode and continues. interrupts that allows to wake up cpu from power - down mode includes external interrupt ? ? ? ? ? ? ? and ? ? ? ? ? ? ? , pin interrupt, wdt interrupt, wkt interrupt, and brown - out interrupt.
N76E003 datasheet jun 26 , 201 7 page 227 of 267 rev. 1.02 23. clock system the N76E003 has a wide variety o f clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. the N76E003 provides three options of the system clock source s including internal oscillator, or external clock from x in pin via software . the N76E003 is embedded with two internal oscillators: one 10 khz low - speed and one 16 mhz high - speed , which is factory trimmed to 2 % under all condition s . a clock divider ckdiv is also available on N76E003 for ad justment of the flexibility between power consumption and operating performance. figure 23 - 1 clock system block diagram 23.1 system clock sources there are a total of three system cloc k sources selectable in the N76E003 including high - speed internal oscillator, low - speed internal oscillator and external clock input. each of them can be the system clock source in the N76E003 . different active system clock source s also affect mul ti - functi on of p 3 .0/x in . i nternal oscillators 23.1.1 there are two internal oscillators in the N76E003 C one 16 mhz high - speed internal oscillator (hirc) and one 10 khz low - speed (lirc) . both of them can be selected as the system clock . hirc can be 1 6 m h z i n t e r n a l o s c i l l a t o r x i n o s c [ 1 : 0 ] ( c k s w t [ 2 : 1 ] ) f o s c c p u p e r i p h e r a l s 1 0 k h z i n t e r n a l o s c i l l a t o r f l a s h m e m o r y f h i r c f l i r c c l o c k d i v i d e r f s y s w a t c h d o g t i m e r c k d i v c l o c k f i l t e r c l o ( p 1 . 1 ) c l o e n ( c k c o n . 1 ) f e c l k 1 0 0 1 0 0 s e l f w a k e - u p t i m e r [ 1 ] d e f a u l t s y s t e m c l o c k s o u r c e a f t e r p o w e r - o n [ 1 ]
N76E003 datasheet jun 26 , 201 7 page 228 of 267 rev. 1.02 enabled by setting hir cen (cken.5). lirc is enabled after device is powered up. user can set osc[ 1 :0] (ckswt [2:1]) as [1 ,1 ] to select the hirc as the system clock . by setting osc[1:0] as [1,0], lirc will be selected as the system clock. note that after the N76E003 is powered, hirc and lirc will be both enabled and hirc is default selected as the system clock source. while using internal oscillator s , x in automatically switch as one general purpose i/o p 3 .0 to expend the number of general purpose i/o. the i/o output mode of p 3 .0 can be selected by configuring p 3 m1 and p 3 m2 registers. 23.2 system c lock switch ing the N76E003 supports clock source switching on - the - fly by controlling ckswt and cken registers via software. it provides a wide flexibility in application. note that these sfrs are writing ta protected for precaution. with this clock source control, the clock source can be switched between the external clock source and the internal oscillator, even between the high and low - speed internal oscillator. however, during clock source s witching, the device requires some amount of warm - up period for an original disabled clock source. therefore, use should follow steps below to ensure a complete clock source switching. user can enable the target clock source by writing proper value into ck en register , wait for the clock source stable by polling its status bit in ckswt register , and switch to the target clock source by changing osc[ 1 :0] (ckswt[2: 1 ]). after these step, the clock source switching is successful and then user can also disable th e original clock source if power consumption is concerned. note that if not following the steps above, the hardware will take certain actions to deal with such illegal operations as follows. 1. if user tries to disable the current clock source by chang ing cken value, the device will ignore this action. the system clock will remain the original one and cken will remain the original value. 2. if user trie s to switch the system clock source to a disabled one by changing osc[1:0] value, osc[1:0] value will be u pdated right away. but the system clock will remain the original one and ckswtf flag will be set by hardware. 3. once user switches the system clock source to a n enabled but still in stable one, the hardware will wait for stabilization of the target clock s ource and then switch to it in the background. during this waiting period, the device will continue executing the program with the original clock source and ckswtf will be set as 1 . after the stable flag of the target clock source (see ckswt[7:3]) is set a nd the clock source switches successfully, ckswtf will be cleared as 0 automatically by hardware.
N76E003 datasheet jun 26 , 201 7 page 229 of 267 rev. 1.02 ckswt C clock switch ( ta protected ) 7 6 5 4 3 2 1 0 - - hircst lircst eclkst osc[1:0] - - - r r r w - address: 96 h reset value: 0011 0000b bit name descri ption 7 - reserved 6 - reserved 5 hirc st high - speed internal oscillator 16 mhz status 0 = high - speed internal oscillator is not stable or disabled. 1 = high - speed internal oscillator is enabled and stable. - - reserved 3 e clkst external clock input st atus 0 = external clock input is not stable or disabled. 1 = external clock input is enabled and stable. 2:1 osc[1:0] oscillator selection bits this field select s the system clock source . 00 = internal 16 mhz oscillator. 01 = external clock source accordi ng to exten[1:0] (cken[7:6]) setting. 10 = internal 10 khz oscillator. 11 = reserved. note that this field is write only. the read back value of this field may not correspond to the present system clock source. ck en C clock enable ( ta protected ) 7 6 5 4 3 2 1 0 exten[1:0] hircen - - - - ckswtf r/w r/w - - - - r address: 97 h reset value: 0011 0000b bit name description 7:6 exten[1:0] external clock source enable 11 = external clock input v ia x in enabled. o thers = external clock input is disable . p 30 wor k as general purpose i/o. 5 hirc en high - speed internal oscillator 16 mhz enable 0 = the high - speed internal oscillator disabled . 1 = the high - speed internal oscillator enabled . note that once iap is enabled by setting iapen (chpcon.0), the high - speed inte rnal 16 mhz oscillator will be enabled automatically. the hardware will also set hirc en and hirc st bits. after iapen is cleared, hirc en and ehrcst resume the original values. 4 :1 - reserved 0 ckswtf clock switch fault flag 0 = the previous system clock s ource switch was successful . 1 = user tried to switch to an in s table or disabled clock source at the previous system clock source switch . if switching to an in stable clock source, this bit remains 1 until the clock source is stable and switching is success ful.
N76E003 datasheet jun 26 , 201 7 page 230 of 267 rev. 1.02 23.3 system clock divider the oscillator frequency (f osc ) can be divided down, by an integer, up to 1/ 510 by configuring a dividing register, ckdiv , to provide the system clock (f sys ) . this feature makes it possible to temporarily run the mcu at a lower r ate, reducing power consumption. by dividing the clock, the mcu can retain the ability to respond to events other than t hose that can cause interrupts ( i.e. events that allow exiting the idle mode ) by executing its normal program at a lower rate. this can often result in lower power consumption than in idle mode. this can allow bypassing the oscillator start - up time in cases where power - down mode would otherwise be used. the value of ckdiv may be changed by the program at any time without interrupting code execution. ckdiv C clock divider 7 6 5 4 3 2 1 0 ckdiv[7:0] r/w address: 95h reset value: 0000 0000b bit name description 7:0 ckdiv[7:0] clock divider the system clock frequency f sys follows the equation below according to ckdiv value. , while ckdiv = 00h, and , while ckdiv = 01h to ffh. 23.4 system clock output the N76E003 provides a clo pin (p 1 . 1 ) that outputs the system clock. its frequency is the same as f sys . the output enable bit is cloen ( ckcon . 1 ). clo outp ut stops when device is put in its power - down mode because the system clock is turned off. note that when noise problem or power consumption is important issue, user had better not enable clo output. reset value: 0000 0000b ckcon C clock control 7 6 5 4 3 2 1 0 - pwmcks - t1m t0m - cloen - - r/w - r/w r/w - r/w - address: 8eh, page: 0 osc sys f = f ckdiv 2 f = f osc sys
N76E003 datasheet jun 26 , 201 7 page 231 of 267 rev. 1.02 bit name description 1 cloen system clock output enable 0 = system clock output disabled. 1 = system clock output enabled from clo pin (p 1 . 1 ).
N76E003 datasheet jun 26 , 201 7 page 232 of 267 rev. 1.02 24. power monitoring to preve nt incorrect execution during power up and power drop, the N76E003 provide two power monitor function s, p ower - on detect ion and brown - out detect ion . 24.1 power - o n reset (por) the power - on detect ion function is design ed for detect ing power up after power voltage reaches to a level where system can work . after power - on detect ed , the po f (pcon. 4) will be set 1 to indicate a cold reset, a power - on reset complete. the p of flag can be cleared via software. pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value : see table 6 - 2 . sfr definitions and reset values bit name description 4 pof power - on reset flag this bit will be set as 1 after a power - on reset. it indicates a cold reset, a power - on reset complete. this bit remains its value after any other resets. this flag is recommended to be cleared via software. notice: N76E003 provides power - on detection to prevent incorrect execution during power up and power drop . the power - on detection function is designed for detecting power up after power voltage reaches to a level where system can work . the N76E003 por - detect - voltage stable s at one value which falls between 1.3 v to 1.5 v. when N76E003 runs in power down mode, the core runs under a low power consumption conditio n. every time N76E003 wakes up from power - down mode, power consumption conditio n changes to normal power consumption. it can cause the core voltage glitch to less than 1.5 v. the por will be trigger , and mcu will reset. workaround: por is for use by vdd power - on. after power - on, the system uses lvr for power detection. strongly suggests that disabl e por function every time after power - on reset at the initial part of customer code. to di sable por: at sfr address, fdh is the pordis register to control disable por function through software.
N76E003 datasheet jun 26 , 201 7 page 233 of 267 rev. 1.02 pordis C por disable ( ta protected ) 7 6 5 4 3 2 1 0 pordis[7:0] w address: fdh, page: 0 reset value: 0000 0000b bit name description 7:0 por dis[7:0] por disable to first writing 5ah to the pordis and immediately followed by a writing of a5h will disable por. since pordis register is ta protected, please always follow list code step to disable por. sfr pordis = 0xfd; ta =0xaa; ta= 0x55; pordis = 0x5a; ta=0xaa ; ta=0x55; pordis = 0xa5; 24.2 brown - o ut detection (bod) the other power monitoring function brown - out detection (bod) circuit is used for monitoring the v dd level during execution. there are eight config selectable brown - out trigger levels available for wi de voltage applications. these eight nominal levels are 2 . 2 v, 2. 7 v, 3 . 7 v a nd 4. 4 v selected via setting c bov[1:0] (config2 [ 5 : 4 ] ). bod level can also be changed by setting bov[1:0] ( bodcon0 [6:4]) after power - on. when v dd drops to the selected brown - out trigg er level (v bod ), the bod logic will either reset the mcu or request a brown - out interrupt. user may decide to being reset or generating a brown - out interrupt according to different applications. v bod also can be set by software after power - on. note that bo d output is not available until 2~3 lirc clocks after software enabling. the bod will request the interrupt while v dd drops below v bod while borst ( bodcon0 . 2 ) is 0. in this case, bof ( bodcon0 .3) will be set as 1 . after user cleared this flag whereas v dd re mains below v bod , bof will not set again. bof just acknowledge user a power drop occurs. the bof will also be set as 1 after v dd goes higher than v bod to indicate a power resuming. the bod circuit provides an useful status indicator bos ( bodcon0 .0), which is helpful to tell a brown - out event or power resuming event occurrence. if the borst bit is set as 1, this will enable brown - out reset function. after a brown - out reset, borf ( bodcon0 .1) will be set as 1 via hardware. it will not be altered by reset other than power - on. this bit can be cleared by s oftware . note that all bits in bodcon0 is writing protected by timed access (ta).
N76E003 datasheet jun 26 , 201 7 page 234 of 267 rev. 1.02 the N76E003 provides low power bod mode for saving current consumption and remaining bod functionality with limited detection resp onse . by setting lpbod [1:0] ( bodcon1 [2:1] ), the bod circuit can be periodically enabled to sense the power voltage nominally every 1.6 ms, 6.4 ms, or 25.6 ms . it saves much power but also provides low - speed power voltage sensing. note that the hysteresis f eature will disappear in low power bod mode. for a noise sensitive system, the N76E003 has a bod filter which filters the power noise to avoid bod event triggering unconsciously. the bod filter is enabled by default and can be disabled by setting bodflt (b odcon1.0) as 0 if user requires a rapid bod response. the minimum brown - out detect pulse width is listed in table 24 - 2 . figure 24 - 1 . br own - o ut detection block diagram config2 7 6 5 4 3 2 1 0 cboden - cbov [1 :0] boiap cborst - - r/w - r/w r/w r/w - - factory default value: 1111 1111b bit name description 7 cboden config brown - out detect enable 1 = b rown - out detection circuit on . 0 = b r own - out detection circuit off . 5 :4 cbov[1:0] config brown - out voltage select 11 = v bod is 2.2 v. 10 = v bod is 2.7 v. 01 = v bod is 3. 7 v. 00 = v bod is 4. 4 v. 2 cborst config brown - out reset enable this bit decides whether a brown - out reset is caused by a powe r drop below v bod . 1 = b rown - out reset enable d . 0 = b rown - out reset disable d . b o v [ 1 : 0 ] b r o w n o u t d e t e c t i o n v d d + - v b o d v o l t a g e s e l e c t b o d e n b o s b o r s t b r o w n - o u t r e s e t b o f b r o w n - o u t i n t e r r u p t o r b o r f l p b o d [ 1 : 0 ] b o d f i l t e r b o d f l t
N76E003 datasheet jun 26 , 201 7 page 235 of 267 rev. 1.02 bodcon0 C brown - out detection control 0 ( ta protected ) 7 6 5 4 3 2 1 0 boden [1] bov[1:0] [1] bof [ 2 ] borst [1] borf bos r/w r/w r/w r/w r/w r address: a3h reset value : see table 6 - 2 . sfr definitions and reset values bit name description 7 boden brown - out detection enable 0 = b rown - out detection circuit off . 1 = b rown - out detection circuit on . note that bod output is not available until 2~3 lirc clocks after enabling. 6 :4 bov[1:0] brown - out voltage select 11 = v bod is 2.2 v. 10 = v bod is 2.7 v. 01 = v bod is 3. 7 v. 00 = v bod is 4. 4 v. 3 bof brown - out interrupt flag this flag will be set as logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod (eie.2) and ea (ie.7) are set, a brown - out interrupt requirement will be generated. this bit should be cleared via software. 2 borst brown - out reset enable this bit decides whether a brown - out reset is caused b y a power drop below v bod . 0 = b rown - out reset when v dd drops below v bod disabled . 1 = b rown - out reset when v dd drops below v bod enabled . 1 borf brown - out reset flag when the mcu is reset by brown - out event, this bit will be set via hardware. this flag is recommended to be cleared via software. 0 bos brown - out status this bit indicates the v dd voltage level comparing with v bod while bod circuit is enabled. it keeps 0 if bod is not enabled. 0 = v dd voltage level is higher than v bod or bod is disabled . 1 = v dd voltage level is lower than v bod . note that t his bit is read - only . [1] boden, bov[1:0] , and borst are initialized by being directly loaded from config 2 bit 7, [ 6 :4], and 2 after all resets. [2] bof reset value depends on different setting of config2 a nd v dd voltage level. please check table 24 - 1 .
N76E003 datasheet jun 26 , 201 7 page 236 of 267 rev. 1.02 table 24 - 1 . bof reset value cboden (config2.7) cborst (config2.2) v dd level bof 1 1 > v bod always 0 1 0 < v bod 1 1 0 > v bod 0 0 x x 0 bodcon 1 C brown - out detection control 1 ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - lpbod[1:0] bodflt - - - - - r/w r/w address: ab h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7:3 - reserved 2:1 lpbod[1:0] low power bod enable 00 = bod n ormal mod e . bod circuit is always enabled. 01 = bod l ow power mode 1 by turning on bod circuit every 1.6 ms periodically. 10 = bod l ow power mode 2 by turning on bod circui t every 6.4 ms periodically. 11 = bod l ow power mode 3 by turning on bod circuit every 25.6 ms periodically. 0 bodflt bod filter control bod has a filter which counts 32 clocks of f sys to filter the power noise when mcu runs with hirc, or eclk as the syst em clock and bod does not operates in its low power mode (lpbod[1:0] = [0, 0]). in other conditions, the filter counts 2 clocks of lirc . note that when cpu is halted in power - down mode. the bod output is permanently filtered by 2 clocks of lirc. the bod fi lter avoids the power noise to trigger bod event. this bit controls bod filter enabled or disabled. 0 = bod filter dis abled. 1 = bod filter en abled. (power - on reset default value.)
N76E003 datasheet jun 26 , 201 7 page 237 of 267 rev. 1.02 table 24 - 2 . minimum b rown - out detect pulse width bodflt (bodcon1.1) bod operation mode system clock source minimum brown - out detect pulse width 0 normal mode (lpbod[1:0] = [0,0]) any clock source typ. 1 s low power mode 1 (lpbod[1:0] = [0, 1 ]) any clock source 16 (1/ f lirc ) low power mode 2 (lpbod[1:0] = [ 1 , 0 ]) any clock source 64 (1/ f lirc ) low power mode 3 (lpbod[1:0] = [ 1 , 1 ]) any clock source 256 (1/ f lirc ) 1 normal mode (lpbod[1:0] = [0,0]) hirc/ eclk normal operation: 32 (1/ f sys ) idle mode: 32 (1/ f sys ) power - down mode: 2 (1/ f lirc ) lirc 2 (1/ f lirc ) low power mode 1 (lpbod[1:0] = [0, 1 ]) any clock source 18 (1/ f lirc ) low power mode 2 (lpbod[1:0] = [ 1 , 0 ]) any clock source 66 (1/ f lirc ) low pow er mode 3 (lpbod[1:0] = [ 1 , 1 ]) any clock source 258 (1/ f lirc )
N76E003 datasheet jun 26 , 201 7 page 238 of 267 rev. 1.02 25. reset the N76E003 has several options to place device in reset condition. it also offers the software flags to indicate the source, which causes a reset. in general, most sfrs go to their res et value irrespective of the reset condition, but there are several reset source indicating flags whose state depends on the source of reset. user can read back these flags to determine the cause of reset using software. there are six ways of putting the d evice into reset state. they are power - on reset, brown - out reset, external reset, hard fault reset, wdt reset, and software reset. 25.1 power - on reset the N76E003 incorporates an internal power - on reset. during a power - on process of rising power supply voltage v dd , the power - on reset will hold the mcu in reset mode when v dd is lower than the voltage reference threshold. this design makes cpu not access program flash while the v dd is not adequate performing the flash reading. if an undetermined operating code is read from the program flash and executed, this will put cpu and even the whole system in to a n erroneous state. after a while, v dd rises above the threshold where the system can work, the selected oscillator will start and then program code will execute fr om 0000h. at the same time, a power - on flag pof (pcon.4) will be set 1 to indicate a cold reset, a power - on reset complete. note that the contents of internal ram will be undetermined after a power - on. it is recommended that user gives initial values for t he ram block. the pof is recommended to be cleared to 0 via software to check if a cold reset or warm reset performed after the next reset occurs. if a cold reset caused by power off and on, pof will be set 1 again. if the reset is a warm reset caused by o ther reset sources, pof will remain 0. user may take a different course to check other reset flags and deal with the warm reset event. pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 4 pof power - on reset flag this bit will be set as 1 after a power - on reset. it indicates a cold reset, a power - on reset complete. this bi t remains its value after any other resets. it is recommended that the flag be cleared via software. 25.2 brown - out reset the b rown - out detection circuit is used for monitoring the v dd level during execution. when v dd drops to the selected brown - out trigger le vel (v bod ), the brown - out detection logic will reset the mcu if
N76E003 datasheet jun 26 , 201 7 page 239 of 267 rev. 1.02 borst ( bodcon0 . 2 ) setting 1. after a brown - out reset, borf ( bodcon0 .1) will be set as 1 via hardware. borf will not be altered by any reset other than a power - on reset or brown - out reset itsel f. this bit can be set or cleared by software. bodcon0 C brown - out detection control 0 ( ta protected ) 7 6 5 4 3 2 1 0 boden - bov[1 :0] bof borst borf bos r/w - r/w r/w r/w r/w r address: a3h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 1 borf brown - out reset flag when the mcu is reset by brown - out event, this bit will be set via hardware. this flag is recommended to be cleared via software. 25.3 external reset and hard fault rese t the external reset pin ? ? ? ? ? ? is an input with a schmitt trigger. an external reset is accomplished by holding the ? ? ? ? ? ? pin low for at least 24 system clock cycles to ensure detection of a valid hardware reset signal. the reset circuitry then synchronous ly applies the internal reset signal. thus, the reset is a synchronous operation and requires the clock to be running to cause an external reset. once the device is in reset condition, it will remain as long as ? ? ? ? ? ? pin is low. after the ? ? ? ? ? ? high is rem oved, the mcu will exit the reset state and begin code exe cuting from address 0000h. if an external reset applies while cpu is in power - down mode, the way to trigger a hardware reset is slightly different. since the power - down mode stops system clock, the reset signal will asynchronously cause the system clock resuming. after the system clock is stable, mcu will enter the reset state. there is a rstpinf (auxr1.6) flag, which indicates an external reset took place . after the external reset, this bit will be set as 1 via hardware. rstpinf will not change after any reset other than a power - on reset or the external reset itself. this bit can be cleared via software. auxr1 C auxiliary register 1 7 6 5 4 3 2 1 0 swrf rstpinf hardf - gf2 uart0px 0 dps r/w r/w r/w - r/w r/w r r/w address: a2h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 6 rstpinf external reset flag when the mcu is reset by the external reset pin , this bit will be set via hardware. it is recommended that the flag be cleared via software.
N76E003 datasheet jun 26 , 201 7 page 240 of 267 rev. 1.02 bit name description 5 hardf hard fault reset flag once program counter (pc) is over flash size , mcu will be reset and this bit will be set via hardware. it is recommended that the flag be cleared via soft ware. note: if mcu run in ocd debug mode and ocden = 0, hard fault reset will be disable d and o nly hardf flag be asserted . 25.4 hard fault reset if program counter (pc) is over flash size , hard fault reset will occur. after hard fault reset , hardf (auxr1. 5 ) flag will be set via hardware. hardf will not change after any reset other than a power - on reset or the hard fault reset itself . this bit can be cleared via software. if mcu run in ocd debug mode and ocden = 0, hard fault reset will be disable d and o nly hardf flag be asserted . 25.5 watchdog timer reset the wdt is a free running timer with programmable time - out intervals and a dedicated internal clock source. user can clear the wdt at any time, causing it to restart the counter. when the selected time - out occ urs but no software response taking place for a while, the wdt will reset the system directly and cpu will begin execution from 0000h. once a reset due to wdt occurs, the wdt reset flag wdtrf (wdcon.3) will be set. this bit keeps unchanged after any reset other than a power - on reset or wdt reset itself. user can clear wdtrf via software. wdcon C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 wdt r wdclr wdtf widpd wdtrf w d ps[2:0] r/w r/w r/w r/w r/w r/w address: aah reset value: see table 6 - 2 . sfr definitions and reset values bit name description 3 wdtrf wdt reset flag when the mcu is reset by wdt time - out event, this bit will be set via hardware. it is recommended that the flag be cleared via software. 25.6 so ftware reset the N76E003 provides a software reset, which allows the software to reset the whole system just similar to an externa l reset, initializing the mcu as it reset state. the software reset is quite useful in
N76E003 datasheet jun 26 , 201 7 page 241 of 267 rev. 1.02 the end of an isp progress. for example , if an isp of boot code updating user code finishes, a software reset can be asserted to re - boot cpu to execute new user code immediately. writing 1 to swrst (chpcon.7) will trigger a software reset. note that this bit is writing ta protection. the instru ction that sets the swrst bit is the last instruction that will be executed before the device reset. see demo code below. if a software reset occurs, swrf (auxr.7) will be automatically set by hardware. user can check it as the reset source indicator. swrf keeps unchanged after any reset other than a power - on reset or software reset itself. swrf can be cleared via software. chpcon C chip control ( ta protected ) 7 6 5 4 3 2 1 0 swrst iapff - - - - bs iapen w r/w - - - - r/w r/w address: 9fh reset value: se e table 6 - 2 . sfr definitions and reset values bit name description 7 swrst software reset to set this bit as logic 1 will cause a software reset. it will automatically be cleared via hardware after reset i s finish ed. auxr1 C auxiliary register 1 7 6 5 4 3 2 1 0 swrf rstpinf hardf - gf2 uart0px 0 dps r/w r/w r/w - r/w r/w r r/w address: a2h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 7 swrf software reset flag when the mcu is reset via software reset, this bit will be set via hardware. it is recommended that the flag be cleared via software. the software demo code is listed below. anl auxr1 ,# 01111111b ; s oftware reset flag clear c lr ea mov ta, # 0a a h mov ta,#55h orl chpcon ,# 10000000b ; s oftware reset
N76E003 datasheet jun 26 , 201 7 page 242 of 267 rev. 1.02 25.7 boot select figure 25 - 1 . boot selecting diagram the N76E003 provides user a flexible boot selection for va riant application. the sfr bit bs in chpcon.1 determines mcu booting from aprom or ldrom after any source of reset. if reset occurs and bs is 0, mcu will reboot from address 0000h of aprom. else, the cpu will reboot from address 0000h of ldrom. note that b s is loaded from the inverted value of cbs bit in config0.7 after all resets except software reset. config0 7 6 5 4 3 2 1 0 cbs - ocdpwm ocden - rpd lock - r/w - r/w r/w - r/w r/w - factory default value: 1111 1111b bit name description 7 cbs config b oot select this bit defines from which block that mcu re - boots after resets except software reset. 1 = mcu will re - boot from aprom after resets except software reset. 0 = mcu will re - boot from ldrom after resets except software reset. chpcon C chip contro l ( ta protected ) 7 6 5 4 3 2 1 0 swrst iapff - - - - bs [1] iapen w r/w - - - - r/w r/w address: 9fh reset value: see table 6 - 2 . sfr definitions and reset values bit name description 1 bs boot select this bit de fines from which block that mcu re - boots after all resets . 0 = mcu will re - boot from aprom after all resets . 1 = mcu will re - boot from ldrom after all resets . r s t p i n r e s e t b r o w n - o u t r e s e t s o f t w a r e r e s e t p o w e r - o n r e s e t l o a d r e s e t a n d b o o t f r o m l d r o m r e s e t a n d b o o t f r o m a p r o m c o n f i g 0 . 7 c h p c o n . 1 w a t c h g o d t i m e r r e s e t b s c b s b s = 0 b s = 1 h a r d f a u l t r e s e t
N76E003 datasheet jun 26 , 201 7 page 243 of 267 rev. 1.02 [1] bs is initialized by being loaded from the inverted value of cbs bit in config0.7 after rese ts except software reset. it keeps unchanged after software reset. after the mcu is released from reset state, the hardware will always check the bs bit instead of the cbs bit to determine from which block that the device reboots. 25.8 reset state the reset st ate besides power - on reset does not affect the on - chip ram. the data in the ram will be preserved during the reset. a fter the power - on reset the ram contents will be indeterminate. after a reset, most of sfrs go to their initial values except bits, which a re affected by different reset events. see the notes of table 6 - 2 . sfr definitions and reset values . the program counter is forced to 0000h and held as long as the reset condition is applied. note that the stack po inter is also reset to 07h and thus the stack contents may be effectively lost during the reset event even though the ram contents are not altered. after a reset, all peripherals and interrupts are disabled. the i/o port latches resumes ffh and i/o mode in put - only.
N76E003 datasheet jun 26 , 201 7 page 244 of 267 rev. 1.02 26. auxiliary features 26.1 dual dptrs the original 8051 contains one dptr (data pointer) only. with single dptr, it is difficult to move data form one address to another with wasting code size and low performance. the N76E003 provides two data pointers. thus, software can load both a source and a destination address when doing a block move. once loading, the software simply switches between dptr and dptr1 by the active data pointer selection dps (auxr1.0) bit. an example of 64 b yte s block move with dual d ptrs is illustrated below. by giving source and destination addresses in data pointers and activating cyclic makes block ram data move more simple and efficient than only one dptr. the inc auxr1 instruction is the shortest (2 bytes) instruction to accompli sh dptr toggling rather than orl or anl . for auxr1.1 contains a hard - wired 0, it allows toggling of the dps bit by incrementing auxr1 without interfering with other bits in the register. mov r0,#64 ;number of bytes to move mov dptr,#d _ addr ;load desti nation address inc auxr1 ;change active dptr mov dptr,#s _ addr ;load source address loop: movx a,@dptr ;read source data byte inc auxr1 ;change dptr to destination movx @dptr,a ;write data to destination inc dptr ;next destination address in c auxr1 ;change dptr to source inc dptr ;next source address djnz r0,loop inc auxr1 ;(optional) restore dps auxr1 also contains a general purpose flag gf2 in its bit 3 that can be set or cleared by the user via software. dpl C data pointer low by te 7 6 5 4 3 2 1 0 dpl[7:0] r/w address: 82h reset value: 0000 0000b bit name description 7:0 dpl[7:0] data pointer low byte this is the low byte of 16 - bit data pointer. dpl combined with dph serve as a 16 - bit data pointer dptr to address non - scratch - p ad memory or program memory. dps (dps.0) bit decides which data pointer, dptr or dptr1, is activated.
N76E003 datasheet jun 26 , 201 7 page 245 of 267 rev. 1.02 dph C data pointer high byte 7 6 5 4 3 2 1 0 dph[7:0] r/w address: 83h reset value: 0000 0000b bit name description 7:0 dph[7:0] data pointer high by te this is the high byte of 16 - bit data pointer. dph combined with dpl serve as a 16 - bit data pointer dptr to address non - scratch - pad memory or program memory. dps (dps.0) bit decides which data pointer, dptr or dptr1, is activated. auxr1 C auxiliary regi ster 1 7 6 5 4 3 2 1 0 swrf rstpinf hardf - gf2 uart0px 0 dps r/w r/w r/w - r/w r/w r r/w address: a2h reset value: see table 6 - 2 . sfr definitions and reset values bit name description 3 gf2 general purpose fla g 2 the general purpose flag that can be set or cleared by the user via software. 1 0 reserved this bit is always read as 0. 0 dps data pointer sele ct 0 = data pointer 0 (dptr) is active by default. 1 = data pointer 1 (dptr1) is active. after dps switche s the activated data pointer, the previous inactivated data pointer remains its original value unchanged. 26.2 96 - b it uid before shipping out, each N76E003 chip was factory pre - programmed with a 96 - bit width serial number, which is guaranteed to be unique. the serial number is called uid . the user can read the u nique code only by iap command . please see iap com mands .
N76E003 datasheet jun 26 , 201 7 page 246 of 267 rev. 1.02 27. on - chip - debugger (ocd) 27.1 functional description the N76E003 is embedded in an on - chip - debugger (ocd) provi ding developers with a low cost method for debugging user code , which is available on each package. the ocd gives debug capability of complete program flow control with eight hardware address breakpoints, single step, free running, and non - intrusive comman ds for memory access. the ocd system does not occupy any locations in the memory map and does not share any on - chip peripherals. when the ocden (config0.4) is programmed as 0 and lock (config0.1) remains un - programmed as 1, the ocd is activated. the ocd ca nnot operate if chip is locked. the ocd system uses a two - wire serial interface, ocdda and ocdck, to establish communication between the target device and the controlling debugger host. ocdda is an input/output pin for debug data transfer and ocdck is an i nput pin for synchronization with ocdda data. the p2.0 / ? ? ? ? ? ? pin is also necessary for ocd mode entry and exit. the N76E003 supports ocd with flash memory control path by icp writer mode, which shares the same three pins of ocd interface. the N76E003 uses ocdda, ocdck, and p2.0 / ? ? ? ? ? ? pins to interface with the ocd system. when designing a system where ocd will be used, the following restrictions must be considered for correct operation: 1. if p2.0 / ? ? ? ? ? ? is configured as external reset pin, it cannot be conn ected directly to v dd and any external capacitors connected must be removed. 2. if p2.0 / ? ? ? ? ? ? is configured as input pin p2.0 , any external input source must be isolated. 3. all external reset sources must be disconnected. 4. any external component connect ed on ocdda and ocdck must be isolated. 27.2 limitation of ocd the N76E003 is a fully - featured microcontroller that multiplexes several functions on its limited i/o pins. some device functionality must be sacrificed to provide resources for ocd system. the ocd has the following limitations: 1. the p2.0 / ? ? ? ? ? ? pin needs to be used for ocd mode selection. therefore, neither p2.0 input nor an external reset source can be emulated.
N76E003 datasheet jun 26 , 201 7 page 247 of 267 rev. 1.02 2. the ocdda pin is physically located on the same pin p 1 . 6 . therefore, neither its i/ o function nor shared multi - functions can be emulated. 3. the ocdck pin is physically located on the same pin as p0. 2 . therefore, neither its i/o function nor shared multi - functions can be emulated. 4. when the system is in idle or power - down mode, it is i nvalid to perform any accesses because parts of the device may not be clocked. a read access could return garbage or a write access might not succeed. 5. hirc cannot be turned off because ocd uses this clock to monitor its internal status. the instruction that turns off hirc affects nothing if executing under debug mode. when cpu enters its power - down mode under debug mode, hirc keeps turning on. the N76E003 ocd system has another limitation that non - intrusive commands cannot be executed at any time while t he users program is running. on - intrusive commands allow a user to read or write mcu memory locations or access status and control registers with the debug controller. a reading or writing memory or control register space is allowed only when mcu is unde r halt condition after a matching of the hardware address breakpoint or a single step running. config0 7 6 5 4 3 2 1 0 cbs - ocdpwm ocden - rpd lock - r/w - r/w r/w - r/w r/w - factory default value: 1111 1111b bit name description 5 ocdpwm pwm output state under ocd halt this bit decides the output state of pwm when ocd halts cpu. 1 = tri - state pins those are used as pwm outputs. 0 = pwm continues. note that this bit is valid only when the corresponding pio bit of pwm channel is set as 1. 4 ocden ocd enabl e 1 = ocd disabled . 0 = ocd enabled . note: if mcu run in ocd debug mode and ocden = 0, hard fault reset will be disable d and o nly hardf flag be asserted .
N76E003 datasheet jun 26 , 201 7 page 248 of 267 rev. 1.02 28. config bytes the N76E003 has several hardware configuration bytes, called config, those are used to configure the hardware options such as the security bits, system clock source, and so on. these hardware options can be re - configured through the parallel writer, in - circuit - programming (icp), or in - application - programming (iap). several functions , which are defined by certain config bits are also available to be re - configured by sfr. therefore, there is a need to load such config bits into respective sfr bits. such loading will occur after resets. these sfr bits can be continuously controlled via users software. config bits marked as - should always keep un - programmed. config0 7 6 5 4 3 2 1 0 cbs - ocdpwm ocden - rpd lock - r/w - r/w r/w - r/w r/w - factory default value: 1111 1111b bit name description 7 cbs config boot select this bit defi nes from which block that mcu re - boots after resets except software reset. 1 = mcu will re - boot from aprom after resets except software reset. 0 = mcu will re - boot from ldrom after resets except software reset. 5 ocdpwm pwm output state under ocd halt thi s bit decides the output state of pwm when ocd halts cpu. 1 = tri - state pins those are used as pwm outputs. 0 = pwm continues. note that this bit is valid only when the corresponding pio bit of pwm channel is set as 1. 4 ocden ocd enabl e 1 = ocd disabled . 0 = ocd enabled . note: if mcu run in ocd debug mode and ocden = 0, hard fault reset will be disable d and o nly hard f flag be asserted . 3 - reserved 2 rpd reset pin disable 1 = the reset function of p2 .0 / nrst pin enabled. p2 .0 / nrst functions as the e xternal reset pin. 0 = the reset function of p2 .0 / nrst pin disabled. p2 .0 / nrst functions as an input - only pin p2 .0 .
N76E003 datasheet jun 26 , 201 7 page 249 of 267 rev. 1.02 bit name description 1 lock chip lock enable 1 = chip is unlocked. flash memory is not locked. their contents can be read out through a parallel writer /icp prog rammer . 0 = chip is locked. whole flash memory is locked. their contents read through a parallel writer or icp programmer will be all blank (ffh). programming to flash memory is invalid. note that config bytes are always unlocked and can be read. hence, on ce the chip is locked, the config bytes cannot be erased or programmed individually. the only way to disable chip lock is execute whole chip erase . however, all data within the flash memory and config bits will be erased when this procedure is executed. if the chip is locked, it does not alter the iap function. figure 28 - 1 . config0 any reset reloading config1 7 6 5 4 3 2 1 0 - - - - - ldsize[2:0] - - - - - r/w factory defa ult value: 1111 1111b bit name description 2:0 ldsize[2:0] ldrom size select part number is N76E003: 111 = no ldrom. aprom is 18k bytes. 110 = ldrom is 1k bytes. aprom is 17k bytes. 101 = ldrom is 2k bytes. aprom is 16k bytes. 100 = ldrom is 3k bytes. apr om is 15k bytes. 0xx = ldrom is 4k bytes. aprom is 14k bytes. config2 7 6 5 4 3 2 1 0 cboden - cbov[ 1 :0] boiap cborst - - r/w - r/w r/w r/w - - factory default value: 1111 1111b bit name description 7 cboden config brown - out detect enable 1 = b rown - out detection circuit on . 0 = b rown - out detection circuit off . 6 - reserved c h p c o n c o n f i g 0 c b s 7 - 6 o c d p w m 5 o c d e n 4 - 3 r p d 2 l o c k 1 - 0 s w r s t 7 i a p f f 6 - 5 - 4 - 3 - 2 b s 1 i a p e n 0 s o f t w a r e r e s e t d o e s n o t r e l o a d
N76E003 datasheet jun 26 , 201 7 page 250 of 267 rev. 1.02 bit name description 5 :4 cbov[ 1 :0] config brown - out voltage select 11 = v bod is 2.2v. 1 0 = v bod is 2.7v. 0 1 = v bod is 3. 7 v. 00 = v bod is 4. 4 v. 3 boiap brown - out inhibiting iap this bit decides wheth er iap erasing or programming is inhibited by brown - out status. this bit is valid only when brown - out detection is enabled. 1 = iap erasing or programming is inhibited if v dd is lower than v bod . 0 = iap erasing or programming is allowed under any workable v dd . 2 cborst config brown - out reset enable this bit decides whether a brown - out reset is caused by a power drop below v bod . 1 = b rown - out reset enable d . 0 = b rown - out reset disable d . figure 28 - 2 . config2 power - on reset reloading config4 7 6 5 4 3 2 1 0 wdten[3:0] - - - - r/w - - - - factory default value: 1111 1111b bit name description 7:4 wdten[3:0] wdt enable this field configures the wdt behavior after mcu execution. 1 111 = wdt is disabled. wdt can be used as a general purpose timer via software control. 0101 = wdt is enabled as a time - out reset timer and it stops running during idle or power - down mode . others = wdt is enabled as a time - out reset timer and it keeps ru nning during idle or power - down mode . 3:0 - reserved b o d c o n 0 c o n f i g 2 c b o d e n 7 c b o v [ 1 : 0 ] 6 5 4 b o i a p 3 c b o r s t 2 - 1 - 0 b o d e n 7 b o v [ 1 : 0 ] 6 5 4 b o f 3 b o r s t 2 b o r f 1 b o s 0 - -
N76E003 datasheet jun 26 , 201 7 page 251 of 267 rev. 1.02 29. in - circuit - programming (icp) the flash memory can be programmed by n - circuit - programming ( p). i f the product is just under development or the end product needs firmware updating in the hand of an end customer, the hardware programming mode will make repeated programming difficult and inconvenient. icp method makes it easy and possible without removing the microcontroller from the system . icp mode also allows customers to manufacture circuit boards with un - programmed devices. programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a customized firmware. there are three signal pins, ? ? ? ? ? ? , icpda , and icpck, involved in icp function. ? ? ? ? ? ? is used to enter or exit icp mode. icpda is the data input and output pin. icpck is the clock input pin, which synchronizes the data shifted in to or out from mcu under programming. user should leave these three pins plus vdd and gnd pins on the circuit board to make icp possible. nuvoton provides icp tool for N76E003 , which enables user to eas ily perform icp through nuvoton icp programmer. the icp programmer developed by nuvoton has been optimized according to the electric characteristics of mcu. it als o satisfies the stability and efficiency during production progress. for more details, please visit nuvoton 8 - bit microcontroller website: nuvoton 80c51 microcontroller technical support .
N76E003 datasheet jun 26 , 201 7 page 252 of 267 rev. 1.02 30. instruction set the N76E003 executes all the instructions of the standard 80c51 family fully compatible with mcs - 51 . however, the timing of each instruction is different for it uses high performance 1 t 8051 core. the architecture eliminates redundant bus states and implements parallel execution of fetching, decode, and execution phases. the N76E003 uses one clock per machine - cycle. it leads to performance improvement of rate 8.1 (in terms of mips) with respect to traditional 12t 80c 5 1 device working at the same clock frequency. however, the real speed improvement seen in any system will depend on the instruction mix. all instructions are coded within an 8 - bit field called an opcode. this single byte sho uld be fetched from program memory. the opcode is decoded by the cpu. it determines what action the cpu will take and whether more operation data is needed from memory. if no other data is needed, then only one byte was required. thus the instruction is ca lled a one byte instruction. in some cases, more data is needed , which is two or three byte instructions. table 30 - 1 lists all instructions for details. the n ote of the instruction set and addressing modes are show n below. rn (n = 0~7) register r0 to r7 of the currently selected register bank. d irect 8 - bit internal data locations address. it could be an internal data ram lo cation (00h to 7fh) or a n sfr (80h to ffh). @r i ( i = 0, 1) 8 - bit internal data ram loc ation (00h to ffh) addressed indirectly through re - gister r0 or r1. #data 8 - bit constant included in the instruction. #data16 16 - bit constant included in the instruction. a ddr16 16 - bit destination address. used by lcall and ljmp. a branch can be a ny - where within the program memory address space. a ddr11 11 - bit destination address. used by acall and ajmp. the branch will be within the same 2 k - byte page of program memory as the first byte of the following i nstruction. r el igned ( s com plement) 8 - bit offset byte . used by sjmp and all conditional branches. the range is - 128 to +127 byte s relative to first byte of the following instruction. b it direct addressed bit in internal data ram or sfr.
N76E003 datasheet jun 26 , 201 7 page 253 of 267 rev. 1.02 table 30 - 1 . instruction set instruction opcode bytes clock cycles N76E003 v.s. tradition 80c51 speed ratio nop 00 1 1 12 add a, rn 28~2f 1 2 6 add a, direct 25 2 3 4 add a, @ri 26, 27 1 4 3 add a, #data 24 2 2 6 addc a, rn 38~3f 1 2 6 add c a, direct 35 2 3 4 addc a, @ri 36, 37 1 4 3 addc a, #data 34 2 2 6 subb a, rn 98~9f 1 2 6 subb a, direct 95 2 3 4 subb a, @ri 96, 97 1 4 3 subb a, #data 94 2 2 6 inc a 04 1 1 12 inc rn 08~0f 1 3 4 inc direct 05 2 4 3 inc @ri 06, 07 1 5 2.4 inc dptr a3 1 1 24 dec a 14 1 1 12 dec rn 18~1f 1 3 4 dec direct 15 2 4 3 dec @ri 16, 17 1 5 2.4 mul ab a4 1 4 12 div ab 84 1 4 12 da a d4 1 1 12 anl a, rn 58~5f 1 2 6 anl a, direct 55 2 3 4 anl a, @ri 56, 57 1 4 3 anl a, #data 54 2 2 6 anl direct , a 52 2 4 3 anl direct, #data 53 3 4 6 orl a, rn 48~4f 1 2 6 orl a, direct 45 2 3 4 orl a, @ri 46, 47 1 4 3 orl a, #data 44 2 2 6 orl direct, a 42 2 4 3 orl direct, #data 43 3 4 6 xrl a, rn 68~6f 1 2 6 xrl a, direct 65 2 3 4 xrl a, @ri 66, 67 1 4 3
N76E003 datasheet jun 26 , 201 7 page 254 of 267 rev. 1.02 table 30 - 1 . instruction set instruction opcode bytes clock cycles N76E003 v.s. tradition 80c51 speed ratio xrl a, #data 64 2 2 6 xrl direct, a 62 2 4 3 xrl direct, #data 63 3 4 6 clr a e4 1 1 12 cpl a f4 1 1 12 rl a 23 1 1 12 rlc a 33 1 1 12 rr a 03 1 1 12 rrc a 13 1 1 12 swap a c4 1 1 12 mov a, rn e8~ef 1 1 12 mov a, direct e5 2 3 4 mov a, @ri e6, e7 1 4 3 mov a, #data 74 2 2 6 mov rn, a f8~ff 1 1 12 mov rn, direct a8~af 2 4 6 mov rn, #data 78~7f 2 2 6 mov direct, a f5 2 2 6 mov direct, rn 88~8f 2 3 8 mov direct, direct 85 3 4 6 mov direct, @ri 86, 87 2 5 4.8 mov direct, #data 75 3 3 8 mov @ri, a f6, f7 1 3 4 mov @ri, direct a6, a7 2 4 6 mov @ri, #data 76, 77 2 3 6 mov dptr, #data16 90 3 3 8 movc a, @a+dptr 93 1 4 6 movc a, @a+pc 83 1 4 6 movx a, @ri [1] e2, e3 1 5 4.8 movx a, @dptr [1] e0 1 4 6 movx @ri, a [1] f2, f3 1 6 4 movx @dptr, a [1] f0 1 5 4.8 push direct c0 2 4 6 pop direct d0 2 3 8 xch a, rn c8~cf 1 2 6 xch a, direct c5 2 3 4 xch a, @ri c6, c7 1 4 3 xchd a, @ri d6, d7 1 5 2.4 clr c c3 1 1 12 clr bit c2 2 4 3
N76E003 datasheet jun 26 , 201 7 page 255 of 267 rev. 1.02 table 30 - 1 . instruction set instruction opcode bytes clock cycles N76E003 v.s. tradition 80c51 speed ratio setb c d3 1 1 12 setb bit d2 2 4 3 cpl c b3 1 1 12 cpl bit b2 2 4 3 anl c, bit 82 2 3 8 anl c, /bit b0 2 3 8 orl c, bit 72 2 3 8 orl c, /bit a0 2 3 8 mov c, bit a2 2 3 4 mov bit, c 92 2 4 6 acall addr11 11, 31, 51, 71, 91, b1, d1, f1 [2] 2 4 6 lcall addr16 12 3 4 6 ret 22 1 5 4.8 reti 32 1 5 4.8 ajmp addr11 01, 21, 41, 61, 81, a1, c1, e1 [3] 2 3 8 ljmp addr16 02 3 4 6 sjmp rel 80 2 3 8 jmp @a+dptr 73 1 3 8 jz rel 60 2 3 8 jnz rel 70 2 3 8 jc rel 40 2 3 8 jnc rel 50 2 3 8 jb bit, rel 20 3 5 4.8 jnb bit, rel 30 3 5 4.8 jbc bit, rel 10 3 5 4 .8 cjne a, direct, rel b5 3 5 4.8 cjne a, #data, rel b4 3 4 6 cjne rn, #data, rel b8~bf 3 4 6 cjne @ri, #data, rel b6, b7 3 6 4 djnz rn, rel d8~df 2 4 6 djnz direct, rel d5 3 5 4.8 [1] the N76E003 does not have external memory bus. movx instructions are used to access internal xram . [2] the most three significant bits in the 11 - bit address [a10:a8] decide the acall hex code. the code will be [a10,a9,a8,1,0,0,0,1]. [3] the most three significant bits in the 11 - bit address [a10:a8] decide the ajmp hex code. the code will be [a10,a9,a8,0,0,0,0,1].
N76E003 datasheet jun 26 , 201 7 page 256 of 267 rev. 1.02 31. electrical character istics 31.1 absolute maximum ratings parameter rating u nit operating temperature under bias (t a ) - 40 to + 10 5 ? c storage temperature range - 55 to +150 ? c voltage on vdd pin to gnd pin - 0.3 to + 6. 3 v voltage on any other pin to gnd pin - 0.3 to (v dd +0.3) v tresses at or above those listed under absolute aximum atings may cause permanent damage to the device. it is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 31.2 d.c. electrical characteristics table 31 - 1 . d.c. electrical characteristics (v dd C v ss = 2.4 ~ 5.5 v, t a = 25 ? c ) symbol parameter condition min. typ. max. unit supply voltage v dd operating v oltage f = 0 to 16 mhz 2.4 - 5.5 v i/o v il input low voltage (i/o with ttl input) v ss - 0. 3 - 0.2v dd - 0.1 v v il1 input low voltage (i/o with schmitt trigger input , ? ? ? ? ? ? , and x in ) v ss - 0. 3 - 0.3v dd v v ih input high voltage (i/o with ttl input) 0.2v dd +0.9 - v dd + 0. 3 v v ih1 input high voltage (i/o with schmitt trigger input and x in ) 0.7v dd - v dd + 0. 3 v v ih2 input high voltage ( ? ? ? ? ? ? ) 0. 8 v dd - v dd + 0. 3 v v ol output low voltage [1] ( normal sink current strength , all modes except input - only) vdd = 5 .5 v, iol = 15 ma - - 0.4 v v dd = 4.5 v, i ol = 1 3 ma - - 0.4 v dd = 3.0 v, i ol = 9 ma - - 0.4 v dd = 2.4 v, i ol = 7 ma - - 0.4
N76E003 datasheet jun 26 , 201 7 page 257 of 267 rev. 1.02 symbol parameter condition min. typ. max. unit v oh output high voltage (quasi - bidirectional mode ) v dd = 5 .5 v, i oh = - 590 ua 2.4 - - v v dd = 4.5 v, i oh = - 38 0 a 2.4 - - v dd = 3.0 v, i oh = - 100 a 2.4 - - v dd = 2.4 v, i oh = - 40 a 2.0 - - v oh1 output high voltage (push - pull mode ) v dd = 5 .5 v, i oh = - 20 ma 2.4 - - v v dd = 4.5 v, i oh = - 1 3 ma 2.4 - - v dd = 3.0 v, i oh = - 3.5 ma 2.4 - - v dd = 2.4 v, i oh = - 2 ma 2.0 - - i il logical 0 input current (quasi - bidirection al mode ) v dd = 5.5 v, v in = 0.4 v - - - 50 a i tl logical 1 - to - 0 transition current [2] (quasi - bidirection al mode ) v dd = 5.5 v -- - - 6 50 a i li input leakage current (open - drain or input - only mode ) - 1 10 a r rst ? ? ? ? ? ? pin internal pull - low resistor 50 - 600 k supply current i dd normal oper ating current [3] hirc - 3.3 3.9 ma lirc - 170 240 a i idl idle mode current hirc 2.2 2.6 ma lirc - 160 230 a i pd power - down mode current (bod off) t a = 25 - 6 8 a t a = - 40 ~ + 10 5 - 20 40 a [1] under steady state (non - transient) con ditions, i ol must be externally limited as follows, maximum i ol per port pin: 1 5 ma maximum total i ol for all outputs: 1 0 0ma [2] pins of all ports in quasi - bidirectional mode source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. [3] t is measured while u keeps in running j p $ loop continuously. all pins of ports are configured as quasi - bidirectional mode.
N76E003 datasheet jun 26 , 201 7 page 258 of 267 rev. 1.02 31.3 a.c. electrical characteristics table 31 - 2 . i/o slew rate a.c. electrical characteristics pxsr.n bit value s ymbol p arameter condition m in . typ. m ax . u nit 0 f out maximum output frequency [ 1 ] v dd = 5.0 v, c l = 30 pf - 34 - mhz v dd = 3.3 v, c l = 30 pf - 22.5 - v dd = 2.4 v, c l = 30 pf - 12.8 - t r output low to high rising time v dd = 5.0 v, c l = 30 pf - 9.7 - ns v dd = 3.3 v, c l = 30 pf - 1 2.5 - v dd = 2.4 v, c l = 30 pf - 1 6.4 - t f output high to low falling time v dd = 5.0 v, c l = 30 pf - 6.6 - ns v dd = 3.3 v, c l = 30 pf - 9.0 - v dd = 2.4 v, c l = 30 pf - 12.3 - 1 f out maximum output frequency [ 1 ] v dd = 5.0 v, c l = 30 pf - 39 - mhz v dd = 3.3 v, c l = 30 pf - 27.5 - v dd = 2.4 v, c l = 30 pf - 17 - t r output low to high rising time v dd = 5.0 v, c l = 30 pf - 9.5 - ns v dd = 3.3 v, c l = 30 pf - 1 2.1 - v dd = 2.4 v, c l = 30 pf - 16 - t f output high to low falling time v dd = 5.0 v, c l = 30 pf - 4. 7 - ns v dd = 3.3 v, c l = 30 pf - 6.2 - v dd = 2.4 v, c l = 30 pf - 8.3 - [1] maximum output frequency is achieved if ((t r + t f ) ) and if the duty cycle is 45% to 55%. ee figure below. figure 31 - 1 . i/o a . c . characteristics def inition t r t f t = 1 / f o u t 1 0 % 9 0 % 9 0 % 1 0 %
N76E003 datasheet jun 26 , 201 7 page 259 of 267 rev. 1.02 table 31 - 3 . internal oscillator a.c. electrical characteristics s ymbol p arameter condition frequency deviation m in . typ. m ax . u nit f hirc high - speed 16 mhz oscillator frequency (hirc) t a = - 10 ~ + 7 0 1 % 15.84 16 16.16 mh z t a = - 40 ~ + 10 5 2 % 15.68 16.32 f lirc low - speed 10 khz oscillator frequency (lirc) t a = + 25 10 % 9 10 11 k hz t a = - 40 ~ + 10 5 [1 ] 35 % 6.5 13.5 [1] this value base on characterization results, not from product test. following shows lirc value under full temperature condition: figure 31 - 2 lirc deviation under v dd = 5.5 v figure 31 - 3 lirc deviation under v dd = 2.4 v following shows hirc accuracy under full temperature condition:
N76E003 datasheet jun 26 , 201 7 page 260 of 267 rev. 1.02 figure 31 - 4 hirc accuracy vs. temperature table 31 - 4 . power - down wake - up a.c. electrical characteristics s ymbol p arameter condition m in . typ. m ax . u nit t pdwk power - down wake - up time hirc - 3 0 - s table 31 - 5 . external reset pin a.c. electrical charact eristics s ymbol p arameter condition m in . typ. m ax . u nit t rst ? ? ? ? ? ? pin de - bounce timing - 24/f sys 450 s . -2.00% -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% -40 -30 -20 -10 0 10 20 25 35 45 55 65 75 85 95 105 115 125 percentage (%) temperature ( ) hirc oscillator accuracy vs. temperature max min
N76E003 datasheet jun 26 , 201 7 page 261 of 267 rev. 1.02 31.4 analog electrical characteristics table 31 - 6 . por electrical characteristics s ymbol p arameter con dition m in . typ. m ax . u nit v por power - on reset voltage 1.3 1.4 1.5 v t p o r rd power - on reset release delay - 5.5 - ms table 31 - 7 . bod electrical characteristics s ymbol p arameter condition m in . typ. m ax . u ni t v bod0 brown - out t hreshold 4.4 v bo v [ 1 :0] = [ 0,0 ] 4.25 4.4 4.55 v v bod 1 brown - out t hreshold 3. 7 v bov[1:0] = [ 0,1] 3.55 3.7 3.85 v v bod 2 brown - out t hreshold 2. 7 v bo v [ 1 :0] = [ 1,0 ] 2. 60 2.7 2.8 0 v v bod 3 brown - out t hreshold 2.2 v bov[1:0] = [1 ,1] 2. 10 2.2 2 .3 0 v v bodhys brown - out hysteresis lpbod[1:0] = [0,0] only - 50 20 0 mv i bod brown - out quiescent current v dd = 5v, lpbod[1:0] = [0,0] - 147 184 a v dd = 5v, lpbod[1:0] = [0,1] - 19 24 v dd = 5v, lpbod[1:0] = [1,0] - 5 7 v dd = 5v, lpbod[1:0] = [1 ,1] - 3 4 t bod brown - out detect pulse width see table 24 - 2 - t bod en brown - out enable time 2 - 3 1/ f lirc table 31 - 8 . band - gap electrical characteristics s ymbol p a rameter condition m in . typ. m ax . u nit v bg band - gap voltage ta = + 25 (4%) 1. 17 1.22 1. 30 v ta = +1 0 ~ + 85 [ 1 ] 1.14 1.3 3 t bgen band - gap enable time 1 - 2 1/ f lirc [1] this value base on characterization results, not from product test.
N76E003 datasheet jun 26 , 201 7 page 262 of 267 rev. 1.02 table 31 - 9 . adc electrical cha racteristics s ymbol p arameter condition m in . typ. m ax . u nit v avdd adc operating voltage 2.7 - 5.5 v i avdd adc power supply current v avdd = 5v - 300 - a v ain analog input voltage 0 - v avdd v n r resolution 12 bit dnl differential non - linearity error - 4 - lsb inl integral non - linearity error - 3 - lsb oe offset error - 2 - lsb tue total un - adjust error - 8 - lsb - monotonicity guaranteed - f c conversion rate 500 k sps fs sampl ing rate [1] 3 80 [ 1 ] k sps t adcen adc enable time 15 us c in adc input equivalent capacitor 3.6 pf [1] this value base on code polling flag. i f call interrupt subroutine need add entry and exit interrupt timing , the sampling rate is about 290 ksps. 31.5 esd characteristics table 31 - 10 esd characteristics symbol ratings condition package m aximum value unit v esd electrostatic discharge (human body m ode ) ta = + 25 tssop 20 qfn 20 7000 v electrostatic discharge ( machine mode) 400 v electrostatic discharge ( de vice charged mode) 1000 v 31.6 eft characteristics table 31 - 11 eft characteristics symbol c ondition package pass level unit fsys bod hirc disable / enable tssop 20 qfn 20 4400 v
N76E003 datasheet jun 26 , 201 7 page 263 of 267 rev. 1.02 31.7 flash dc electrical characteristics table 31 - 12 flash dc electrical characteristics symbol parameter min. typ. max. unit condition v fla supply voltage 1.62 1.8 1.98 v n endur endurance 100,000 - - cycle t ret data retention - 50 - year ta = + 25 - 40 - year ta = + 5 5 10 - year ta = + 8 5 t erase page erase time - 5 - ms 1 page t prog program time - 10 - us 1 byte i dd1 read current - 4 - ma i dd2 program current - 4 - ma i dd3 erase current - 2 - ma
N76E003 datasheet jun 26 , 201 7 page 264 of 267 rev. 1.02 32. package dimensions 32.1 20 - pin tssop - 4.4 x 6.5 mm figure 32 - 1 . tssop - 20 package dimension
N76E003 datasheet jun 26 , 201 7 page 265 of 267 rev. 1.02 32.2 20 - pin qfn C 3.0 x 3.0 mm figure 32 - 2 . qfn - 20 package dimension
N76E003 datasheet jun 26 , 201 7 page 266 of 267 rev. 1.02 33. document revision history revision date description v1.00 201 6 / 10 / 28 initial release v1.01 2017/6/12 chapter 31. 3 add ed hirc accuracy vs. temperature figure . chapter 31.4 m odif ied band - gap max value from 1.27 to 1.30 . chapter 13. 5 modified sfr name to rctrim0 and rctrim1 for modify hirc application . chapter 24.1 a dd ed disable por function after power on description . chapter 31.7 modified d ata rete ntion value at 25 condition, add ed co ndition at 55 and 85 data. v1.02 2017/6/26 chapter 18.1.4 added chapter description of band - gap as adc input to calculate the vdd value. chapter 15.3 added how to clear si register example code for i 2 c transmission issue.
N76E003 datasheet jun 26 , 201 7 page 267 of 267 rev. 1.02 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , ns ecure usage. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all nsecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of custom ers nsecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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